Data Type Scaling Strip — Control Systems/Signal Attributes
Control_Systems/Signal_Attributes/Data_Type_Scaling_Strip · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Data Type Scaling Strip
Control Systems / Signal Attributes
Hands its input on with the signal's scaling removed – y = u. A scaled fixed-point signal relates a stored integer to the real-world value it stands for through a slope and a bias; stripping the scaling discards that relation and passes on the stored integer as a plain number.
On this tree's signals that is the identity, and the block says so rather than pretending otherwise. Every ICore wire carries a matrix of doubles, a double is its own real-world value, and a slope of one with a bias of zero is exactly what "no scaling" means – so there is nothing for the strip to remove and the output equals the input, sample for sample. This is what Simulink's own block does to a signal of that kind; it is not a simplification of it.
Ports
- Input – the signal u, of any size [m,n].
- Output – y, always the SAME size [m,n] as the input and carrying the same values.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. This one is ICore's own: the Simulink block defines no dialog parameters at all, not even a sample time, so a rate set here stays on the ICore side and is reported rather than written into an exported model.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every one of them emits a straight copy, and none of them carries the strip itself – whatever scaling a signal had was resolved when the model was built, so a deployed core would be removing something that is no longer there. The three HDL targets are therefore trivially synthesizable: there is no arithmetic to quantize.
Simulink bridge
Import and export, mapped to simulink/Signal Attributes/Data Type Scaling Strip.
There are no parameter pairs, because the Simulink block has no parameters: measured in
R2026a, its dialog-parameter list comes back empty. That includes
SampleTime, so the bridge deliberately does not write one – setting a
parameter a Simulink block does not define is a hard error that aborts the whole generated
script. A block configured with an explicit positive rate reports that the rate did not
cross.
Notes
- Algebraic, with no state: the output is the input, sample for sample.
- Deliberately carries no state space, even though the identity is linear. Absorbing this block into a neighbour would erase a marker the user put on the wire on purpose, so model reduction reports it as unmergeable instead – the same choice Signal Specification makes.
- If you are looking for a block that CHANGES a value to fit a narrower type – rounding it and clamping or wrapping it at the type's limits – that is Data Type Conversion, not this one. This block changes no value at all.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Attributes/Data_Type_Scaling_Strip |
| family | Control_Systems/Signal_Attributes |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Data_Type_Scaling_Strip |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Data_Type_Scaling_Strip/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Data_Type_Scaling_Strip.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Data_Type_Scaling_Strip/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Data_Type_Scaling_Strip.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Attributes/Data Type Scaling Strip |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the Simulink block has NO dialog parameters at all -- measured in R2026a, get_param(blk,'DialogParameters') comes back empty -- so there is nothing to map and nothing that can be lost in either direction; the strip itself is the identity on an ICore signal, every wire here carrying a matrix of doubles, which is a real-world value with no slope and no bias to remove
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Data Type Scaling Strip -- hand the signal on with its scaling removed y = u. See the header for why that is the FAITHFUL reading of Simulink's block rather than a stub: the strip removes a slope and a bias, and a double carries neither.
All ten exports are a straight copy, and none of them carries the strip itself. There is nothing to carry: whatever scaling an incoming signal had was already gone when the model was built, so a deployed core would be re-removing something that is not there.
Measured in R2026a: get_param on this block returns an EMPTY DialogParameters -- no parameters at all, SampleTime included. The catalog entry says so with hasSampleTimeParam = false, because set_param on a name a block does not define aborts the generated script rather than warning.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.