Data Type Propagation — Control Systems/Signal Attributes

Control_Systems/Signal_Attributes/Data_Type_Propagation · 3 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Data Type Propagation

Control Systems / Signal Attributes

Derives a data type from the types of two reference signals, by a rule for its signedness, its word length and its scaling, and demands it of a third signal. The third signal's source takes that type when it is set to inherit its type by back propagation – a Data Type Conversion with Output data type Inherit: Inherit via back propagation. A source that names another type is a mismatch and the run is refused: the block never converts anything. It computes nothing and has no output; Simulink's block is virtual, and so is this one.

Ports

Ref1 – the first reference. Its type is read and its value is not. A boolean reads as uint8, an integer as a fixed-point type of its width with slope 1.
Ref2 – the second reference, read the same way.
Prop – the signal whose type is set: it accepts the derived type and nothing else.

Parameters

Propagated Data Type Mode – Inherit via propagation rule (the default) or Specify via dialog, which takes the sign and the word length from Propagated Data Type instead of the rule, even when a reference is floating-point.
Propagated Data Type – a fixdt(s, w) or fixdt(s, w, f), default fixdt(1, 16). The scaling still follows Propagated Scaling Mode, as in Simulink: a fraction length written here is the scaling only when that mode is Specify via dialog, where it takes the place of Propagated Scaling.
If Any Reference Is Double and If Any Reference Is Single – under the rule, a double reference makes the result this type (default double), and otherwise a single one makes it that one (default single).
Is Signed – IsSigned1, IsSigned2, IsSigned1 or IsSigned2 (the default), TRUE or FALSE.
Number Of Bits Base – NumBits1, NumBits2, max([NumBits1 NumBits2]) (the default), min([NumBits1 NumBits2]) or NumBits1+NumBits2; the word length is this times Number Of Bits Multiplicand (default 1) plus Number Of Bits Addend (default 0), at least 2 bits when signed and 1 when not.
Allowable Number Of Bits – -1 (the default) allows any word length; a list such as [8 16 32] rounds the word length up to the smallest entry that holds it, and a word length above every entry is refused.
Propagated Scaling Mode – Inherit via propagation rule (the default), Specify via dialog (the slope is Propagated Scaling, default 2^-10, a number or 2^k) or Obtain via best precision (the finest power-of-two slope at which every value of Values For Best Precision, default [5 -7], fits the word).
Slope Base – Slope1, Slope2, max, min([Slope1 Slope2]) (the default), Slope1*Slope2, Slope1/Slope2, or the same six over PosRange1 and PosRange2, a type's range 2^(w−s)·slope, divided by the new type's 2^(w−s). The slope is this times Slope Multiplicand (default 1) plus Slope Addend (default 0).
Bias Base – Bias1 (the default), Bias2, max, min, Bias1*Bias2, Bias1/Bias2, Bias1+Bias2 or Bias1-Bias2, times Bias Multiplicand (default 1) plus Bias Addend (default 0). Every ICore type has bias 0.
Sampling Time (s) – not used: the block computes nothing. It does not cross to Simulink, whose block has no rate parameter.

When a run is refused

A reference that is not connected or is not a number; input 3 driven by a source of another type; a word length above every allowable one; and a result ICore's types cannot hold – a slope that is not a power of two, a nonzero bias, a word over 53 bits or a fraction length beyond ±64.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, as a named body that does nothing. The type was settled before the export, and the source it was demanded of carries it in the exported code.

Simulink bridge

Import and export, mapped to simulink/Signal Attributes/Data Type Propagation, every parameter 1:1 and lossless, the choices spelled as Simulink spells them: Propagated Data Type Mode ↔ PropDataTypeMode, Propagated Data Type ↔ PropDataType, If Any Reference Is Double ↔ IfRefDouble, If Any Reference Is Single ↔ IfRefSingle, Is Signed ↔ IsSigned, Number Of Bits Base ↔ NumBitsBase, Number Of Bits Multiplicand ↔ NumBitsMult, Number Of Bits Addend ↔ NumBitsAdd, Allowable Number Of Bits ↔ NumBitsAllowFinal, Propagated Scaling Mode ↔ PropScalingMode, Propagated Scaling ↔ PropScaling, Values For Best Precision ↔ ValuesUsedBestPrec, Slope Base ↔ SlopeBase, Slope Multiplicand ↔ SlopeMult, Slope Addend ↔ SlopeAdd, Bias Base ↔ BiasBase, Bias Multiplicand ↔ BiasMult, Bias Addend ↔ BiasAdd. A scaling written as 2^-3 crosses as written. The Simulink block has no SampleTime.

Notes

The demand reaches a source set to back propagation, through subsystem boundaries, as ICore's back propagation reaches any consumer. A source with a type of its own is checked against the demand and never changed.
To check that signals share a type without deriving one, use Data Type Duplicate; to change a type, Data Type Conversion.
Verified against R2026a: every one of 169 reference pairs (double, single, boolean, the six integers and four fixdt types) and 270 rule settings gives the type R2026a's block gives, where ICore can hold it.

Code facts#

Fact	Value
registered type	`Control_Systems/Signal_Attributes/Data_Type_Propagation`
family	`Control_Systems/Signal_Attributes`
solver environment class	`ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Data_Type_Propagation`
source	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Data_Type_Propagation/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Data_Type_Propagation.cpp`
header	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Data_Type_Propagation/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Data_Type_Propagation.h`
default size on canvas	90 × 90 px
ports at insert	3 in, 0 out
code generators implemented	`Python`, `MATLAB`, `Java`, `Rust`, `C`, `C++`, `VHDL`, `Verilog`, `SystemVerilog`, `PLC Structured Text`

Ports#

#	Direction	Signal type	Description label
1	in	`ICoreDouble`	Ref1
2	in	`ICoreDouble`	Ref2
3	in	`ICoreDouble`	Prop

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variable	Default	Simulink parameter
`Propagated Data Type Mode`	`Specify via dialog%~%Inherit via propagation rule~~Inheri…`	`PropDataTypeMode`
`Propagated Data Type`	`fixdt(1, 16)`	`PropDataType`
`If Any Reference Is Double`	`double%~%single~~double`	`IfRefDouble`
`If Any Reference Is Single`	`double%~%single~~single`	`IfRefSingle`
`Is Signed`	`IsSigned1%~%IsSigned2%~%IsSigned1 or IsSigned2%~%TRUE%~%F…`	`IsSigned`
`Number Of Bits Base`	`NumBits1%~%NumBits2%~%max([NumBits1 NumBits2])%~%min([Num…`	`NumBitsBase`
`Number Of Bits Multiplicand`	`1`	`NumBitsMult`
`Number Of Bits Addend`	`0`	`NumBitsAdd`
`Allowable Number Of Bits`	`-1`	`NumBitsAllowFinal`
`Propagated Scaling Mode`	`Specify via dialog%~%Inherit via propagation rule%~%Obtai…`	`PropScalingMode`
`Propagated Scaling`	`2^-10`	`PropScaling`
`Values For Best Precision`	`[5 -7]`	`ValuesUsedBestPrec`
`Slope Base`	`Slope1%~%Slope2%~%max([Slope1 Slope2])%~%min([Slope1 Slop…`	`SlopeBase`
`Slope Multiplicand`	`1`	`SlopeMult`
`Slope Addend`	`0`	`SlopeAdd`
`Bias Base`	`Bias1%~%Bias2%~%max([Bias1 Bias2])%~%min([Bias1 Bias2])%~…`	`BiasBase`
`Bias Multiplicand`	`1`	`BiasMult`
`Bias Addend`	`0`	`BiasAdd`

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#


support	`Support::Both`
Simulink path	`simulink/Signal Attributes/Data Type Propagation`
port-count rule	`PortsParam::None`
`SampleTime` parameter	no — the counterpart defines none; the rate stays on the ICore side

ICore config	Simulink parameter	Value translation
`Propagated Data Type Mode`	`PropDataTypeMode`	`Specify via dialog` → `Specify via dialog`, `Inherit via propagation rule` → `Inherit via propagation rule`
`Propagated Data Type`	`PropDataType`	passes through
`If Any Reference Is Double`	`IfRefDouble`	`double` → `double`, `single` → `single`
`If Any Reference Is Single`	`IfRefSingle`	`double` → `double`, `single` → `single`
`Is Signed`	`IsSigned`	`IsSigned1` → `IsSigned1`, `IsSigned2` → `IsSigned2`, `IsSigned1 or IsSigned2` → `IsSigned1 or IsSigned2`, `TRUE` → `TRUE`, `FALSE` → `FALSE`
`Number Of Bits Base`	`NumBitsBase`	`NumBits1` → `NumBits1`, `NumBits2` → `NumBits2`, `max([NumBits1 NumBits2])` → `max([NumBits1 NumBits2])`, `min([NumBits1 NumBits2])` → `min([NumBits1 NumBits2])`, `NumBits1+NumBits2` → `NumBits1+NumBits2`
`Number Of Bits Multiplicand`	`NumBitsMult`	passes through
`Number Of Bits Addend`	`NumBitsAdd`	passes through
`Allowable Number Of Bits`	`NumBitsAllowFinal`	passes through
`Propagated Scaling Mode`	`PropScalingMode`	`Specify via dialog` → `Specify via dialog`, `Inherit via propagation rule` → `Inherit via propagation rule`, `Obtain via best precision` → `Obtain via best precision`
`Propagated Scaling`	`PropScaling`	passes through
`Values For Best Precision`	`ValuesUsedBestPrec`	passes through
`Slope Base`	`SlopeBase`	`Slope1` → `Slope1`, `Slope2` → `Slope2`, `max([Slope1 Slope2])` → `max([Slope1 Slope2])`, `min([Slope1 Slope2])` → `min([Slope1 Slope2])`, `Slope1Slope2` → `Slope1Slope2`, `Slope1/Slope2` → `Slope1/Slope2`, `PosRange1` → `PosRange1`, `PosRange2` → `PosRange2`, `max([PosRange1 PosRange2])` → `max([PosRange1 PosRange2])`, `min([PosRange1 PosRange2])` → `min([PosRange1 PosRange2])`, `PosRange1PosRange2` → `PosRange1PosRange2`, `PosRange1/PosRange2` → `PosRange1/PosRange2`
`Slope Multiplicand`	`SlopeMult`	passes through
`Slope Addend`	`SlopeAdd`	passes through
`Bias Base`	`BiasBase`	`Bias1` → `Bias1`, `Bias2` → `Bias2`, `max([Bias1 Bias2])` → `max([Bias1 Bias2])`, `min([Bias1 Bias2])` → `min([Bias1 Bias2])`, `Bias1Bias2` → `Bias1Bias2`, `Bias1/Bias2` → `Bias1/Bias2`, `Bias1+Bias2` → `Bias1+Bias2`, `Bias1-Bias2` → `Bias1-Bias2`
`Bias Multiplicand`	`BiasMult`	passes through
`Bias Addend`	`BiasAdd`	passes through

Caveat (shown to the user): the block is virtual on both sides; every parameter crosses under its own name, and the Simulink block has NO SampleTime, so a rate set here does not cross

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:

B0 no sample under docs/generated/samples/ — nothing to cross-check (P8.1)

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Data Type Propagation -- a type derived from two references, demanded of a third signal simulink/Signal Attributes/Data Type Propagation, MEASURED on R2026a (FEATURES_TO_ADD.md §F.BF14: BF14.1 by fx4, and 2026-10-02 by icoreblocks-0e over 169 reference pairs and 270 rule settings): MaskType "Data Type Propagation", an S-Function (sfix_dtprop, compiled), 3 in and 0 out, virtual. Inputs 1 and 2 are REFERENCES -- their types are read, their values not -- and the rule's result is demanded of the signal on input 3, whose source must leave its own type open ("Inherit: Inherit via back propagation"); a source that states another type is a mismatch, never a conversion.

The rule, as measured (every row of the two sweeps reproduced):

FLOATING: with "Inherit via propagation rule", a double reference gives IfRefDouble's

choice, otherwise a single one gives IfRefSingle's -- double beats single.

Otherwise a fixed-point type: a boolean reference reads as uint8; an integer as fixdt(s,w,0).

sign by IsSigned (IsSigned1, IsSigned2, either, TRUE, FALSE), or the dialog type's; width by NumBitsBase (NumBits1, NumBits2, max, min, NumBits1+NumBits2) * NumBitsMult + NumBitsAdd, at least 2 bits signed and 1 unsigned, then rounded UP to the smallest NumBitsAllowFinal value (-1: any) -- none large enough is an error -- or the dialog type's width; slope by SlopeBase (Slope1, Slope2, max, min, Slope1*Slope2, Slope1/Slope2) * SlopeMult + SlopeAdd, a float reference's slope being 1; the PosRange forms read a type's range 2^(w-s)*slope and divide the result by the new type's 2^(w-s); "Specify via dialog" takes PropScaling, and best precision the largest fraction length at which every value in ValuesUsedBestPrec fits ((2^(w-s)-1)/v for v > 0, 2^(w-1)/|v| for v < 0 when signed, a negative ignored when unsigned); bias by BiasBase over the references' biases * BiasMult + BiasAdd.

"Specify via dialog" (PropDataType, a fixdt) gives the sign and the width, and applies even

to float references; scaling still follows PropScalingMode (BF14.1's trap, reproduced), and under PropScalingMode "Specify via dialog" a fraction length written in PropDataType is the scaling, in place of PropScaling (fixdt(0,10,3) with 2^-5 compiles to ufix10_En3).

A result with slope 1 and width 8, 16, 32 or 64 is the integer type of that width.

ICore carries binary-point fixdt only (BF14.2), so a slope that is not a power of two, a nonzero bias, a word over 53 bits or a fraction beyond +/-64 is refused by name.

THE DEMAND: input 3 accepts the derived type alone, and ICoreModelBuild's back propagation gives a back-propagated source the one type its consumers accept -- with the fixdt this block names on its input's carrier when that type is ICoreFixed. The block is registered as settling its input types late, so its loadBlockConfig() runs before back propagation, with its references' types settled.

Sample results#

No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.

Data Type Propagation — Control Systems/Signal Attributes

Description#