Data Type Duplicate — Control Systems/Signal Attributes
Control_Systems/Signal_Attributes/Data_Type_Duplicate · 2 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Data Type Duplicate
Control Systems / Signal Attributes
Checks that every signal reaching it has the same data type as the signal on its first input, and refuses the run when one does not. It computes nothing and has no outputs: it is a statement about the diagram, made before the first step.
Ports
- Inputs 1 … N – the signals whose types must agree, one or
more; add or remove inputs from the block's port settings. Input 1 is the
reference. Any data type is accepted – double, single, any integer width,
bool, string, complex, fixed point or an enumeration – and the sizes may
differ: only the type is compared. A fixed-point signal's
fixdtand an enumeration's type name are part of its type. A bus, a function call and a message are not accepted. - No outputs.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate. Nothing depends on it, since the block produces nothing. It does not cross to Simulink, whose block has no rate parameter.
When a run is refused
As Simulink refuses it: Data type mismatch. 'Input Port 2' of '…' expects a signal of data type 'double'. However, it is driven by a signal of data type 'int32'. An input that is not connected is not checked.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The check is made before the export, which a mismatch stops; each target then holds a named body that does nothing, which is all the block does in generated code (Simulink's block is virtual and emits none).
Simulink bridge
Import and export, mapped to simulink/Signal Attributes/Data Type
Duplicate. The number of inputs crosses as NumInputPorts. The
rate does not cross.
Notes
- Only the check. In Simulink this block also gives an input whose type is inherited the shared type, propagating it backwards. ICore does not: a source set to inherit its type from where it is used takes ICore's default here, and the check then compares that.
- To change a type rather than check it, use Signal Attributes / Data Type Conversion.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Attributes/Data_Type_Duplicate |
| family | Control_Systems/Signal_Attributes |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Data_Type_Duplicate |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Data_Type_Duplicate/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Data_Type_Duplicate.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Data_Type_Duplicate/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Data_Type_Duplicate.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 2 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | in | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Attributes/Data Type Duplicate |
| port-count rule | PortsParam::DataTypeDuplicateInputs |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the input count crosses as
NumInputPorts; the block is virtual on both sides and has NO SampleTime parameter, so a rate set here does not cross
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Data Type Duplicate -- all inputs carry the first input's data type, or the run is refused Measured on R2026a (2026-10-02):
simulink/Signal Attributes/Data Type Duplicate, one dialog parameterNumInputPorts(default 2; 1 is accepted, 0 is "must be finite and positive"), N in and ZERO out, no SampleTime (set_param is Simulink:Commands:ParamUnknown). A double and an int32 into it refuse the run with Simulink:DataType:InputPortDataTypeMismatch, "Data type mismatch. 'Input Port 2' of 'dtd_p/D' expects a signal of data type 'double'. However, it is driven by a signal of data type 'int32'." -- the FIRST input is the reference; a single and a boolean are refused the same way; two doubles of different SIZES run. The block is virtual (BLOCKS_TO_ADD_SIMULINK_FAMILIES.md, wq8's measurement): it contributes nothing to a run or to generated code.Since typed ports (PORT_TYPES.md) the check is real here: a source keeps its own type, read off getConnectionSource(), as Compose String reads it. An enumeration's project type and a fixed-point port's fixdt are part of the type, as they are in Simulink.
NOT carried: Simulink also gives an input declared as inherited the shared type (it propagates the type backwards). ICore's back-propagation (BF14.3) settles an inherited source from the types its consumers ACCEPT, and this block accepts every type, so nothing settles from it. The description says so.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.