Downsample — Control Systems/Resampling

Downsample

Control Systems / Resampling

Keeps one sample in every K and holds it until the next one is kept, so the output runs at the block's own rate rather than at a slower one:

y[k] = u[k] when k mod K = offset, and y[k] = y[k−1] on the K−1 samples in between. Before the first kept sample – that is, while k < offset – the block emits its Initial Condition. The sample index k counts from 0 at the start of the run.

Ports

• Input – the signal u to decimate, of any size [m,n]. Every entry is latched and held on the same samples; the block does not stagger them and the entries do not interact.
• Output – the decimated-and-held signal y, the SAME size [m,n] as the input.

Parameters

• Downsampling Factor – K, the number of samples in one period. A whole number of 1 or more; at K = 1 every sample is kept and the block is a wire. Defaults to 2.
• Sample Offset – which sample of each period is the kept one, as a whole number from 0 to K−1. At 0 the very first sample of the run is kept and the initial condition is never seen; at a larger value the block emits the initial condition for exactly that many samples first. Defaults to 0.
• Initial Condition – a scalar, what the block emits before the first kept sample. It is broadcast to every entry of the signal, so one value seeds a matrix signal whatever its size. Defaults to 0, and is only ever visible when the offset is nonzero.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. On this block it also sets what one "sample" means: K counts steps of this rate, so the retained stream comes out at one Kth of it.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The factor and the offset are baked into the core at export time rather than exposed as tunable parameters: they are structural, and a decimator whose period could be retuned on a built core would be a different block. The initial condition is baked in for the same reason – it seeds a state rather than scaling arithmetic.

The three HDL targets are not simulation-only here: the block does no arithmetic at all, so a core is an enable-gated register plus a small counter, and the Q-format word is copied rather than computed on – not one bit of it is disturbed between the input port and the output. What those columns do still carry is the port's own quantization, which is a property of an HDL signal and not of this block: measured over a 1001-sample export-verification run, the three of them come back at 0.00076–0.00095 % residual, the same figures a block that only passes its input through scores in the same run, while all seven software targets are exact at residual 0.

What every target does have to write the same way is the kept sample: it publishes the input directly rather than reading the register it is storing into, because an HDL register write is deferred to the clock edge and reading it back in the same tick would return the PREVIOUS kept sample.

Simulink bridge

Import and export, mapped to dspsigops/Downsample – the DSP System Toolbox block, not a core Simulink one. "Downsampling Factor" to DownsamplingFactor, "Sample Offset" to SampleOffset and "Initial Condition" to InitialConditions, all three pass-through.

Three of that block's parameters are always emitted with a fixed value, because this block offers no choice behind them: FactorSource = Dialog parameter (the factor is a config here, never a port), InputProcessing = Elements as channels (sample based) and RateOptions = Enforce single-rate processing. That last pair is what makes the crossing exact: it is the one configuration in which the Simulink block's output port runs at its input's rate, which is the only kind of block an ICore wire can carry.

"Sampling Time (s)" does not cross. dspsigops/Downsample defines no SampleTime parameter at all – verified against the R2026a block dialog – and set_param on a parameter a block does not define is a hard error in MATLAB that aborts the whole generated script rather than degrading. The rate stays on the ICore side, and a block configured with an explicit positive rate reports that it did not cross.

Notes

• Stateful: the retained sample and the phase counter. Both start from the configured initial condition and 0 at the beginning of every run, so a re-run reproduces the stream exactly.
• Discrete by nature – the phase advances once per sample, so the block always takes its period from its own "Sampling Time (s)" and is never pushed through a continuous solver's intermediate stages.
• Downsample vs. Zero-Order Hold. Both hold a value between updates, and the difference is what decides when an update happens. Zero-Order Hold updates on its own "Sampling Time (s)" – a period in seconds – and has neither a phase nor a seed. Downsample updates every Kth sample of the rate it is running at, counts that phase from the start of the run, and carries an initial condition for the samples before the first update. Reach for the first to model a sampler and for this one to decimate a stream by a whole factor.
• No anti-alias filter. This block keeps samples; it does not filter first, so anything above half the retained rate folds back into the band exactly as it does in the Simulink block. Put a low-pass in front of it if that matters.
• It is not MATLAB's downsample function, which returns a SHORTER vector. A wire cannot get shorter, so the retained samples are held instead – which is what the Simulink block does, and what this block is compared against.