Decimate — Control Systems/Resampling

Decimate

Control Systems / Resampling

Low-pass filters a stream and then keeps one sample in every D, holding each retained sample until the next one, so the output runs at the block's own rate rather than at a slower one. The filter runs on every sample; only its publication is decimated:

w[k] = c₀·u[k] + c₁·u[k−1] + … + c_n·u[k−n], then y[k] = w[k] when k mod D = 0 and y[k] = y[k−1] on the D−1 samples in between. The sample index k counts from 0 at the start of the run, so the very first sample is always a retained one, and the filter's delay line starts empty.

The filter is what separates this block from Downsample: anything above half the retained rate folds back into the band when it is not removed first.

Ports

• Input – the signal u to filter and decimate, of any size [m,n]. Every entry is filtered and retained on the same samples, each carrying its own delay line; the entries do not interact.
• Output – the filtered-and-held signal y, the SAME size [m,n] as the input.

Parameters

• FIR Coefficients – c₀…c_n, the anti-alias filter's impulse response as a non-empty vector, first entry multiplying the current sample and last the oldest. This block does not design the filter: pair it with FIR Window Design, or pass a response designed elsewhere. Defaults to [0.25 0.5 0.25], the three-tap half-band smoother that suits the default factor of 2.
• Decimation Factor – D, the number of samples in one period, a whole number of 1 or more. At D = 1 every filtered sample is published and the block is a plain FIR filter. Defaults to 2.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. On this block it also sets what one "sample" means: D counts steps of this rate, so the retained stream comes out at one Dth of it.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The coefficients and the factor are baked into the core at export time rather than exposed as tunable parameters: the tap count also fixes how many state words the core carries, and a decimator whose period could be retuned on a built core would be a different block.

The three HDL targets are not simulation-only. The arithmetic is one multiply-accumulate over a short constant tap list, which the Q16.16 datapath carries without difficulty; what those columns do carry is the port's own quantization, which is a property of an HDL signal rather than of this block. Measured over a 1001-sample export-verification run at four taps and factor 3, the three of them come back at 0.0031–0.0036 % residual while the software targets are exact or within one double rounding (0 to 1.2×10 ⁻¹⁴ %). The delay line is emitted unrolled, so a long filter on a large signal is a large entity: the state word count is n×m×p for a filter with n taps behind the current sample on an [m,p] signal, plus one word per signal entry for the retained sample.

What every target writes the same way is the retained sample: it publishes the freshly computed sum directly rather than reading back the register it is storing into, because an HDL register write is deferred to the clock edge and reading it in the same tick would return the previous retained sample.

Simulink bridge

Import and export, mapped to dspmlti4/FIR Decimation – the DSP System Toolbox block, not a core Simulink one. "FIR Coefficients" to h and "Decimation Factor" to D, both pass-through.

Five of that block's parameters are always emitted with a fixed value, because this block offers no choice behind them: FilterSource = Dialog parameters (the taps are a config here, never a port and never a filter object), filtStruct = Direct form, InputProcessing = Elements as channels (sample based), framing = Enforce single-rate processing and outputBufInitCond = 0. That middle pair is what makes the crossing exact: it is the one configuration in which the Simulink block's output port runs at its input's rate, which is the only kind of block an ICore wire can carry. The last one is pinned rather than mapped because it is unobservable in that configuration – with no phase offset the first sample is itself a retained one, and a run at 0 and a run at −9 are identical to the digit.

"Sampling Time (s)" does not cross. dspmlti4/FIR Decimation defines no SampleTime parameter at all – verified against the R2026a block dialog – and set_param on a parameter a block does not define is a hard error in MATLAB that aborts the whole generated script rather than degrading. The rate stays on the ICore side, and a block configured with an explicit positive rate reports that it did not cross.

Notes

• Stateful: the filter's delay line, the retained sample and the phase counter. All three start from zero at the beginning of every run, so a re-run reproduces the stream exactly.
• Discrete by nature – the phase advances once per sample, so the block always takes its period from its own "Sampling Time (s)" and is never pushed through a continuous solver's intermediate stages.
• No state space, deliberately. The filter alone would be linear, but which sample is published depends on WHEN it arrives, so no single A/B/C/D describes the block and fabricating one would let the model-reduction commands absorb it into a neighbour as a filter that publishes everything.
• It is not MATLAB's decimate function, which filters with a forward-and-backward pass that is not causal and then returns a SHORTER vector. A stream can carry neither, so the filter here is the ordinary causal one and the retained samples are held.