Chebyshev Type I Design — Control Systems/Polynomials

Chebyshev Type I Design

Control Systems / Polynomials

Designs a digital Chebyshev Type I filter of order N and reports its coefficients, with the cutoff arriving on a port. It is MATLAB's cheby1: the analog equiripple-passband prototype, denormalized to the cutoff and mapped to z by the bilinear transform prewarped at that same cutoff, so the passband edge sits at exactly f_c.

A Type I filter trades ripple in the passband for a steeper transition than a Butterworth of the same order. Everything follows from one number, T = tan(πf_c/f_s); both polynomials are then divided by a[0], so the denominator is monic and the answer is MATLAB's exactly.

It designs; it does not filter. Feed b and a to Discrete / Transfer Fcn Direct Form II Time Varying, which takes them on ports and so retunes with them.

Ports

• fc – the passband-edge frequency in Hz, the point at which the response has fallen by the full ripple. Scalar. Clamped into (0, f_s/2) – see Notes, the clamp is a live branch.
• b – the numerator's coefficients, descending powers of z, as a column of N + 1 entries.
• a – the denominator's, the same length, with a[0] = 1.

Parameters

• Order – N, a whole number from 1 to 8. Both outputs are N + 1 long. Default 3.
• Filter Type – which prototype mapping is used:
  • Lowpass – passes below the cutoff. Default.
  • Highpass – passes above it. The same prototype with s and 1/s exchanged, which swaps the roles of (z−1) and (z+1).
• Passband Ripple (dB) – R_p, the peak-to-peak depth of the passband ripple in decibels. Strictly positive, from 1e−4 to 60. A smaller value flattens the passband and softens the transition; a larger one does the reverse. Default 1.5.
• Sample Rate (Hz) – f_s, the rate the filter is designed FOR, and the rate the cutoff is measured against. Strictly positive. This is not the block's own rate. Default 100.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The order, the type, the ripple and the rate are structural and are baked into the generated body, so nothing is exposed as a tunable parameter on the generated core; the prototype coefficients and the integer expansions are inlined.

The three HDL targets are simulation-only, and deliberately: a tangent and a reciprocal do not belong in a Q16.16 datapath. Both are evaluated in real and the values convert at the port boundary, which is what the Trigonometry family does for the same reason. The seven software targets are exact.

Simulink bridge

None (Support::None). cheby1 is a MATLAB function, and the two Simulink blocks that carry a Chebyshev Type I design – Analog Filter Design and Lowpass IIR Filter Design, both in the DSP System Toolbox's design library – do the design internally and expose no part of it: each takes a signal in and gives a filtered signal out, so neither has coefficients a diagram could read. There is therefore no library path this block could name. The bridge reports it rather than dropping it silently, and it has no parity testbench; code export verification still covers it across all ten languages. No configuration of it crosses either, including "Sampling Time (s)", which has no counterpart to be written to.

Notes

• Algebraic, with no state: the output depends only on the current input.
• The even-order response does not start at 1. A Type I response of odd order is 1 at zero frequency; one of even order starts a whole ripple low, at 10^−R_p/20. That is cheby1's convention, and it is carried here rather than normalized away – a block that forced both to 1 would scale every numerator coefficient by a constant, leave the poles exactly right, and differ from MATLAB in a way a response plot does not show.
• The clamp is a live branch, not a safety net. f_c is clamped into (0, f_s/2) by (|x−lo| − |x−hi| + lo + hi)/2, branchless and identical in this block and in all ten emitted bodies, so they agree bit for bit. It exists because VHDL's TAN raises an error at π/2, which stops a simulation rather than returning a bad number. A cutoff at or below zero therefore designs at the bottom of the band rather than failing: T → 0, the numerator collapses and the denominator becomes (z−1)^N. The committed documentation sample shows it at f_c = 0 – every entry of b below 4e−23, against a = [1, −3, 3, −1] to eight digits.
• Dividing by a[0] is safe here, and it is not on Bilinear Transform. a[0] is a sum of d_j·T^… terms with every d_j and T strictly positive, so it cannot vanish. Polynomials / Bilinear Transform takes its analog denominator from a port, where the same quantity can pass through zero, so that block leaves the scale alone.
• Measured against R2026a, at f_s = 4 Hz over orders 1 to 8, cutoffs 0.7 Hz and 1.1 Hz and both types: the largest disagreement with cheby1 on any coefficient is 6.8e−14 at order 8, and 8.9e−16 at order 3. The expansion is less well conditioned as the order rises, which is what that spread measures.
• No state space: one scalar in and two vectors out, so there is no A/B/C/D to merge and model reduction correctly declines it.