Check Static Lower Bound — Control Systems/Model Verification
Control_Systems/Model_Verification/Check_Static_Lower_Bound · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Check Static Lower Bound
Control Systems / Model Verification
Verifies that a signal never falls below a constant floor, and publishes the verdict as a signal: y = 1 where the entry passes, y = 0 where it fails. The test is u ≥ min when Include Minimum is on and u > min when it is off. Applied entry by entry, so a matrix signal is checked element for element.
Ports
- Input – the signal u under test, of any size [m,n].
- Output – the verdict y, of the SAME size [m,n]: one 1.0/0.0 flag per entry of u. The block never reshapes a signal.
Parameters
- Minimum – scalar, the floor the signal is held to. A per-entry bound sized like the input is not implemented and is reported rather than broadcast from its first entry; for a bound that varies per entry or over time, use Check Dynamic Lower Bound, which takes it on a port.
- Include Minimum – whether a sample sitting exactly ON the bound
passes.
- on – the test is u ≥ min (the default).
- off – the test is u > min, so the bound itself fails.
- Enabled – whether a failing sample is REPORTED. It does not
change the output signal: an entry that fails still reads 0 with this off, which
is what Simulink's counterpart does.
- on – a failure is logged once per run, with the block's path and the time it first happened (the default).
- off – the block computes its verdict silently.
- Stop When Assertion Fails – whether a reported failure also ends
the run.
- on – the run stops at the first failing sample and is marked failed (the default).
- off – the run continues and the failure is a warning.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. The bound and the choice of ≥ versus
> are baked into the generated code at export time rather than
exposed as tunable parameters, matching the other comparison blocks. Only the
VERDICT SIGNAL is exported: Enabled and Stop When Assertion Fails
have no meaning in a deployed core, which has no simulation to stop, so a core
computes the flag and leaves acting on it to whatever consumes the signal.
Simulink bridge
Import and export, mapped to simulink/Model Verification/Check Static
Lower Bound. "Minimum" to min and "Include Minimum" to
min_included, "Enabled" to enabled and "Stop When
Assertion Fails" to stopWhenAssertionFail, all as plain
pass-through values, so the round trip is lossless. The block always sets
Simulink's export to on: ICore's block always has its
verdict output, whereas Simulink's grows one only when that box is ticked, so
importing a block with it unticked reports the difference rather than silently
dropping the port. The Simulink counterpart has no
SampleTime parameter, so "Sampling Time (s)" does not cross –
the block runs at the surrounding Simulink rate.
Notes
- Algebraic, with no signal state. The only state is a one-shot latch so that a failing run logs its complaint once rather than once per sample.
- Not linear, and so deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing a comparison.
- The comparison is one-sided: only the LOWER side is checked, and an arbitrarily large input passes. Pair it with Check Static Upper Bound, or use Check Static Range, to bound both sides.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Model_Verification/Check_Static_Lower_Bound |
| family | Control_Systems/Model_Verification |
| solver environment class | ICoreBlock_0_Control_Systems_1_Model_Verification_2_Check_Static_Lower_Bound |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Model_Verification/Check_Static_Lower_Bound/ICoreBlock_0_Control_Systems_1_Model_Verification_2_Check_Static_Lower_Bound.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Model_Verification/Check_Static_Lower_Bound/ICoreBlock_0_Control_Systems_1_Model_Verification_2_Check_Static_Lower_Bound.h |
| default size on canvas | 80 × 80 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Minimum | 0 | min |
Include Minimum | on%~%off~~on | min_included |
Enabled | on%~%off~~on | enabled |
Stop When Assertion Fails | on%~%off~~on | stopWhenAssertionFail |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Model Verification/Check Static Lower Bound |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | export = on |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Minimum | min | passes through |
Include Minimum | min_included | passes through |
Enabled | enabled | passes through |
Stop When Assertion Fails | stopWhenAssertionFail | passes through |
Caveat (shown to the user): the block runs at the surrounding Simulink rate; "Sampling Time (s)" does not cross. ICore's block always carries its verdict output, so the bridge pins Simulink's "export" to on
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Check Static Lower Bound -- verifies a signal stays at or above a constant floor y = 1 where the entry passes the test, 0 where it does not. The test is u >= min with "Include Minimum" on and u > min with it off. Applied entry by entry, so the output keeps the input's size.
The verdict SIGNAL and the ASSERTION are two separate things, and only the first crosses into generated code:
- the signal is what the output port carries, what the ten backends emit, and what code
export verification compares;
- the assertion is a simulator-side diagnostic -- "Enabled" decides whether a failure is
reported at all, "Stop When Assertion Fails" whether it also ends the run. Verified against Simulink R2026a: toggling
enabledthere leaves the exported assertion signal bit-identical, so ICore keeping the two apart matches the reference rather than diverging from it.Code export: the bound and the comparison are inlined as export-time constants, per language. The two assertion controls are NOT exported -- a deployed core has no simulation to stop.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | 0 | 1 |
| 0.4 | 0 | 1 |
| 0.8 | 0 | 1 |
| 1.2 | 1 | 1 |
| 1.6 | 1 | 1 |
| 2 | 1 | 1 |
| 2.4 | 1 | 1 |
| 2.8 | 1 | 1 |
| 3.2 | 1 | 1 |
| 3.6 | 1 | 1 |
| 4 | 1 | 1 |
| 4.4 | 1 | 1 |
| 4.8 | 1 | 1 |
| 5.2 | 1 | 1 |
Every 4th of 60 samples, from the step stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 1 … 1 |
ramp | Ramp: slope 1 from t = 0 | 1 … 1 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Model_Verification__Check_Static_Lower_Bound.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).