Generated reference › Check Discrete Gradient — Control Systems/Model Verification
kind: generated#block#control-systems-model-verification

Check Discrete Gradient — Control Systems/Model Verification

Control_Systems/Model_Verification/Check_Discrete_Gradient · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Check Discrete Gradient

Control Systems / Model Verification

Verifies that a signal never jumps by more than a given amount from one sample to the next, and publishes the verdict: y = 1 where the entry passes, y = 0 where it fails. The test is |u[k] − u[k−1]| < gradient, taken entry by entry.

Note what that is not: it is a raw difference between samples, not a rate of change. The sampling period does not divide into it, so the same signal checked at a faster rate passes more easily – which is Simulink's behaviour, measured, and not an ICore simplification.

Ports

  • Input – the signal u under test, of any size [m,n]. Each entry is tracked independently against its own previous value.
  • Output – the verdict y, of the SAME size [m,n]: one 1.0/0.0 flag per entry.

Parameters

  • Maximum Gradient – scalar, the largest step the signal may take between consecutive samples. Defaults to 1, as in Simulink. The comparison is strict: a step of exactly this size FAILS.
  • Enabled – whether a failing sample is REPORTED. It does not change the output signal: an entry that fails still reads 0 with this off, which is what Simulink's counterpart does.
    • on – a failure is logged once per run, with the block's path and the time it first happened (the default).
    • off – the block computes its verdict silently.
  • Stop When Assertion Fails – whether a reported failure also ends the run.
    • on – the run stops at the first failing sample and is marked failed (the default).
    • off – the run continues and the failure is a warning.
    Ignored entirely when Enabled is off.
  • Sampling Time (s) – the block is inherently discrete, so this is the period at which it takes its samples. A non-positive value falls back to the model's global sampling time. Because the test is a raw difference, this parameter changes the VERDICT and not merely the update rate: the same signal sampled twice as fast takes half-sized steps and passes more easily.

Notes on the first sample

The first sample of a run always passes: there is no previous value to difference against, so the block seeds its memory from u[0] itself and the first difference is exactly zero. It is deliberately not seeded from zero, which would fail the first sample of any signal that does not start at the origin. Measured against Simulink, which behaves the same way.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. This is the only block in the family with persistent state, so every backend carries the previous sample plus a "primed" flag – the flag is what reproduces the first-sample rule above, and a core that dropped it would disagree with the reference on exactly one sample. The gradient is baked in as an export-time constant rather than exposed as a tunable parameter.

Simulink bridge

Import and export, mapped to simulink/Model Verification/Check Discrete Gradient. "Maximum Gradient" to gradient, "Enabled" to enabled and "Stop When Assertion Fails" to stopWhenAssertionFail, all as plain pass-through values, so the round trip is lossless. The block always sets Simulink's export to on: ICore's block always has its verdict output, whereas Simulink's grows one only when that box is ticked. The Simulink counterpart has no SampleTime parameter, so "Sampling Time (s)" does not cross – and on this block that is worth knowing, because the rate changes the verdict. Set the rate on the Simulink side by the surrounding model.

Notes

  • Stateful, and the state is one previous sample per entry.
  • Discrete only: the block declares itself discrete, so a model running a continuous solver still steps it once per sample rather than pushing it through Runge-Kutta, where "the previous sample" would be meaningless.
  • Not linear, and so deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing a comparison.

Code facts#

FactValue
registered typeControl_Systems/Model_Verification/Check_Discrete_Gradient
familyControl_Systems/Model_Verification
solver environment classICoreBlock_0_Control_Systems_1_Model_Verification_2_Check_Discrete_Gradient
sourcesrc/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Model_Verification/Check_Discrete_Gradient/ICoreBlock_0_Control_Systems_1_Model_Verification_2_Check_Discrete_Gradient.cpp
headersrc/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Model_Verification/Check_Discrete_Gradient/ICoreBlock_0_Control_Systems_1_Model_Verification_2_Check_Discrete_Gradient.h
default size on canvas80 × 80 px
ports at insert1 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDouble
2outICoreDouble

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Maximum Gradient1gradient
Enabledon%~%off~~onenabled
Stop When Assertion Failson%~%off~~onstopWhenAssertionFail

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::Both
Simulink pathsimulink/Model Verification/Check Discrete Gradient
port-count rulePortsParam::None
SampleTime parameterno — the counterpart defines none; the rate stays on the ICore side
always setexport = on
ICore configSimulink parameterValue translation
Maximum Gradientgradientpasses through
Enabledenabledpasses through
Stop When Assertion FailsstopWhenAssertionFailpasses through

Caveat (shown to the user): the block runs at the surrounding Simulink rate; "Sampling Time (s)" does not cross, which matters more here than elsewhere because the test is a raw difference between samples and so the RATE changes the verdict. ICore's block always carries its verdict output, so the bridge pins Simulink's "export" to on

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Check Discrete Gradient -- verifies the input never jumps by more than a given amount y = 1 where |u[k] - u[k-1]| < gradient, 0 elsewhere. Entry by entry, so the output keeps the input's size.

Three measured properties, each easy to get wrong plausibly (see the header):

  • RAW difference, NOT divided by Ts;
  • STRICT -- a step of exactly gradient fails;
  • the FIRST sample always passes, because prev is seeded from u[0] rather than from 0.

The last of those is what the primed flag exists for, in the live solver AND in all ten generated backends. Seeding prev from zero instead is the classic wrong version: it agrees with the reference on every sample except the first, which is exactly the kind of one-sample disagreement that reads as a tolerance problem rather than a logic error.

Discrete-only: "the previous sample" has no meaning under a continuous solver that evaluates a step several times, so the block declares setDiscreteOnlyBlock(true).

Sample results#

Check Discrete Gradient — Sine Wave: amplitude 1, 2 rad/s, no phase, no biasCheck Discrete Gradient — Sine Wave: amplitude 1, 2 rad/s, no phase, no bias0.90.9511.051.1-0.500.5inputoutput
tin ICoreDouble-Out-0out ICoreDouble-Out-0
001
0.40.71741
0.80.99961
1.20.67551
1.6-0.058371
2-0.75681
2.4-0.99621
2.8-0.63131
3.20.11651
3.60.79371
40.98941
4.40.58491
4.8-0.17431
5.2-0.82781

Every 4th of 60 samples, from the sine stimulus.

The same rig also ran:

StimulusWhat it isOutput range
rampRamp: slope 1 from t = 01 … 1

Plotted: sine — Sine Wave: amplitude 1, 2 rad/s, no phase, no bias

Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Model_Verification__Check_Discrete_Gradient.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).