Send — Control Systems/Messages And Events
Control_Systems/Messages_And_Events/Send · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Send
Control Systems / Messages And Events
Turns a signal into messages: on each of its sample hits it sends one message carrying the input’s value u, stamped with the time it was sent, on a message line. A message is consumed where it is read – by a Receive, or by a message-triggered subsystem, which runs once for each one – rather than held like a sample. With its enable port shown, it sends only on the hits whose enable is positive.
Ports
- Input u – the value each message carries, any size [m,n]. With Show enable port On it is the second input.
- Input enable – only with Show enable port On, and then the first input, as in Simulink: a message goes out on the hits where any element is greater than zero; zero and negative values send nothing.
- Output msg – a message line, whose messages are the size of u. It connects only to a block that reads messages (a Receive, or a message Trigger port’s face) and never branches.
Parameters
- Show enable port – Off (default): one input, a message on every hit. On: two inputs, the enable then u. The input count must agree: add or remove the port to match, or the run is refused with the block’s name.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
Python, MATLAB, Java, Rust, C and C++: the message line is one fixed-capacity queue in the generated core, held beside the signals, and it keeps its reader’s policy (a Receive’s queue, or a message-triggered subsystem’s). Each call copies u to the output and pushes it onto the line’s queue (with the enable shown, when any element of the enable is positive).
VHDL, Verilog, SystemVerilog and PLC Structured Text refuse a message line by name: a hardware queue is left until a hardware design asks for one. A message line that crosses the boundary of the subsystem being exported is refused by every target.
Simulink bridge
Import and export, mapped to simulink/Messages & Events/Send.
Show enable port ↔ ShowEnablePort (Off/On ↔
off/on, lossless), and Simulink moves the enable port itself. "Sampling Time
(s)" does not cross: Simulink’s Send has no
SampleTime parameter and runs at its input’s rate, so give the
signal feeding it that rate; a rate set here stays on the ICore side and is
reported.
Notes
- Stateless: each hit sends what u is then. Several messages wait on the line until their reader takes them; what is kept when they pile up is the reader’s choice (a Receive’s queue).
- Measured on R2026a: an enable of 1, −1, 0, 2, −3 on successive hits sends on the first and the fourth.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Messages_And_Events/Send |
| family | Control_Systems/Messages_And_Events |
| solver environment class | ICoreBlock_0_Control_Systems_1_Messages_And_Events_2_Send |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Messages_And_Events/Send/ICoreBlock_0_Control_Systems_1_Messages_And_Events_2_Send.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Messages_And_Events/Send/ICoreBlock_0_Control_Systems_1_Messages_And_Events_2_Send.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++ |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreMessage | msg |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Show enable port | Off%~%On~~Off | ShowEnablePort |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Messages\n& Events/Send |
| port-count rule | PortsParam::SendEnablePort |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Show enable port | ShowEnablePort | Off → off, On → on |
Caveat (shown to the user): Simulink's Send has no SampleTime: it runs at its input's rate.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 3 entries for 2 ports (1 in, 1 out), and the 3 they cover does not reconcile — grouped, or one undocumented? a reader must sayB0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.