Message Merge — Control Systems/Messages And Events

Message Merge

Control Systems / Messages And Events

Joins message lines: every message that arrives on any input is passed on, on the one output, and none is dropped here. Messages sent in the same step leave in the order their senders ran, which is the order Simulink’s sorted execution gives – not the order of the input ports; one sent in an earlier step leaves first. What the reader keeps is the reader’s: a Receive without its internal queue keeps only the last message of a step, a Queue or a Receive’s internal queue keeps them all.

Ports

• Input u1 … uN – message lines, two by default; add or remove inputs to change N. Their messages are all the same size [m,n].
• Output msg – the message line with every message that arrived.

Parameters

• None of its own: the number of inputs is the number of input ports.
• Sampling Time (s) – zero or less (default) inherits its senders’ rate, so it passes each message on as it is sent; a positive value runs it at that period, and messages wait on its inputs between its hits.

Code export

Python, MATLAB, Java, Rust, C and C++: each message line is one fixed-capacity queue in the generated core, held beside the signals; each input’s queue keeps every message, and each call moves them all to the output’s, those of senders that run after this block (sent in the step before) first, then the rest, each in its senders’ order, as live.

VHDL, Verilog, SystemVerilog and PLC Structured Text refuse a message line by name: a hardware queue is left until a hardware design asks for one. A message line that crosses the boundary of the subsystem being exported is refused by every target.

Simulink bridge

Import and export, mapped to simulink/Messages & Events/Message Merge; the number of input ports ↔ NumberInputPorts. "Sampling Time (s)" does not cross: Simulink’s Message Merge has no SampleTime parameter; a rate set here stays on the ICore side and is reported.

Notes

• The messages may be a bus (a Hit Crossing Probe’s); every input’s messages must then be the same bus, and a bus beside a matrix is refused with the block’s name.
• Stateless: it keeps no message from one step to the next.
• Measured on R2026a: two Sends of 100+t and 200+t through a Message Merge into a FIFO Queue are read 100, 200, 101, 201, …, the first sender first whatever port it takes; straight into a Receive with no queue, only the last of each step reaches it (200, 201, 202). Simulink’s block Priority can reorder the senders; ICore has no block priority.