Transpose — Control Systems/Matrix Operations
Control_Systems/Matrix_Operations/Transpose · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Transpose
Control Systems / Matrix Operations
Exchanges the input's rows and columns: y = uT, so an [m,n] signal leaves as an [n,m] one. Element (i,j) of the output is element (j,i) of the input; nothing is scaled.
Ports
- Input – the matrix u, of any size [m,n].
- Output – [n,m]. This is one of the few blocks whose output dimensions differ from its input's, and the only thing that decides them is the input's shape.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
There is nothing else to set: a transpose has no choices, and the Simulink counterpart offers none either.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The copy is unrolled at export time from the settled port sizes, so the generated core carries no loop bounds to get wrong.
The three HDL targets are fully synthesizable. A transpose is pure data movement, so the values stay in the Q16.16 datapath and nothing is converted at the port boundary or approximated.
Simulink bridge
Import and export, mapped to simulink/Matrix Operations/Transpose. There are no parameters to carry: the Simulink block is a masked subsystem whose dialog is empty.
It defines no SampleTime parameter, so the rate is
not carried across: it stays on the ICore side, and a block configured
with an explicit positive rate reports that the rate did not cross.
Simulink's neighbouring Hermitian Transpose is a different block – it conjugates – and is not what this one maps to.
Notes
- Algebraic, with no state – pure signal reindexing.
- Deliberately carries no state space, even though the transpose is linear: it reshapes, and a D matrix can rescale a signal but never re-index one.
- Computes what Permute Dimensions does at the order [2 1], and what Math Function's Transpose operator does. All three are separate blocks in Simulink, in three different libraries, and separate here, so a model imports onto the one it was drawn with.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Matrix_Operations/Transpose |
| family | Control_Systems/Matrix_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Transpose |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Transpose/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Transpose.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Transpose/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Transpose.h |
| default size on canvas | 90 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Matrix Operations/Transpose |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the Simulink counterpart is a masked subsystem with no dialog parameters at all, so the mapping carries the block and nothing else; its neighbour Hermitian Transpose is a DIFFERENT block (it conjugates) and is not what this maps to
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Transpose -- y = u.', the rows and columns of the input exchanged Measured against Simulink R2026a on [1 2 3; 4 5 6]:
[2,3] 1 2 3 -> [3,2] 1 4 4 5 6 2 5 3 6
The Simulink counterpart is a masked subsystem with NO dialog parameters whatsoever - not even SampleTime - so the mapping carries nothing but the block itself.
HDL is SYNTHESIZABLE: a transpose is pure data movement, so the values stay in the Q16.16 datapath and nothing is converted at the port boundary or approximated.
Algebraic and stateless. No state space -- see the header for why.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Matrix_Operations__Transpose.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).