IsTriangular — Control Systems/Matrix Operations
Control_Systems/Matrix_Operations/IsTriangular · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
IsTriangular
Control Systems / Matrix Operations
A test, not a transform: the output is 1 when everything on the far side of the main diagonal is exactly zero, and 0 when any of it is not.
- Upper – every entry below the diagonal is zero: u(i,j) = 0 for i > j.
- Lower – every entry above the diagonal is zero: u(i,j) = 0 for i < j.
The entries ON the diagonal and on the chosen side are never looked at, so they may hold anything, zeros included. A diagonal matrix therefore passes both tests – it has nothing off either side – and so does a matrix of all zeros. Simulink's block answers the same way.
The input need not be square, which is where this block differs from IsSymmetric and IsHermitian: those return 0 for any non-square input, while a non-square matrix can perfectly well be triangular. A 3×2 whose two sub-diagonal entries are zero is upper triangular here and in Simulink.
Ports
- u – the matrix to test, of any size [m,n].
- Output – a 1×1 signal carrying 1 or
0. ICore has no boolean signal type – every signal is a double
– so the verdict arrives as those two values rather than as a logical.
Simulink's block emits a genuine
boolean, which is the one difference across the bridge and costs nothing, since 1 and 0 are what a boolean compares equal to.
Parameters
- Triangular Part – which side must be zero. This selects the code
path rather than retuning one, so each option is a separate branch in all ten
export targets.
- Upper – the entries below the diagonal must be zero, leaving an upper-triangular matrix. The default, as in Simulink.
- Lower – the entries above the diagonal must be zero.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing is exposed as a tunable parameter: which entries are checked is structural and is fixed into the generated code at export time, as one explicit comparison per entry rather than a call to each language's own triangular helper. Where the input's SHAPE already decides the answer – a single row is always upper triangular, a single column always lower – every target emits the constant instead of a comparison. The three HDL targets are fully synthesizable: exact comparisons against zero and two constants, with no arithmetic.
The HDL cores test QUANTIZED values, which is worth knowing before reading a red row. An HDL port carries Q16.16, so an entry smaller than one quantum (1.5×10−5) arrives as exactly 0 and the hardware answers 1 where the reference answers 0. An entry that is zero by CONSTRUCTION – a signal multiplied by a zero gain, say – quantizes to zero on every target and is unaffected.
Simulink bridge
Import and export, mapped to simulink/Matrix Operations/IsTriangular.
"Triangular Part" goes to Mode, one option for one option
(Upper, Lower), so that round trip is lossless.
The rate does NOT cross: Simulink's IsTriangular defines only
Mode, with no SampleTime, so the entry sets
hasSampleTimeParam = false and "Sampling Time (s)" stays on the
ICore side. Writing that parameter anyway would be a hard set_param
error in MATLAB rather than a warning, aborting the whole generated script.
Notes
- Algebraic, with no state: the output depends only on the current input.
- The comparison is EXACT, as Simulink's is – neither side has a tolerance parameter, and "zero" means exactly zero rather than "small". A matrix whose sub-diagonal was computed to zero rather than built that way will usually fail, an elimination step leaving rounding dust behind it.
- No state space: the block is a comparison, not a linear map, so no D·u represents it and model reduction reports it as unmergeable.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Matrix_Operations/IsTriangular |
| family | Control_Systems/Matrix_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_IsTriangular |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/IsTriangular/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_IsTriangular.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/IsTriangular/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_IsTriangular.h |
| default size on canvas | 75 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Triangular Part | Upper%~%Lower~~Upper | Mode |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Matrix Operations/IsTriangular |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Triangular Part | Mode | Upper → Upper, Lower → Lower |
Caveat (shown to the user): the rate does not cross: Simulink's IsTriangular defines only Mode, with no SampleTime, so "Sampling Time (s)" stays on the ICore side. Simulink's output is a genuine boolean where ICore's is a 1/0 double, every ICore signal being a double.
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
IsTriangular block -- 1 when the far side of the main diagonal is all zeros Two tests, chosen by "Triangular Part": Upper every entry BELOW the diagonal is exactly zero: u(i,j) = 0 for i > j Lower every entry ABOVE the diagonal is exactly zero: u(i,j) = 0 for i < j
ANY SHAPE, NOT JUST SQUARE, which is where this block parts company with its two neighbours. Symmetry needs a square matrix; being triangular does not, and that was confirmed against the real Simulink block rather than assumed -- fed the 3x2 [1 2; 0 3; 0 0] its Upper mode answers true. So a non-square input here is a real test with a real answer, not the automatic 0 that IsSymmetric and IsHermitian return for one.
A DIAGONAL MATRIX PASSES BOTH TESTS, and that is correct rather than a loophole: the constraints are on the entries OFF the chosen side, and a diagonal matrix has nothing on either. Simulink agrees -- diag([1 3]) answers true in Upper mode.
THE COMPARISON IS EXACT, as Simulink's is: neither block has a tolerance parameter, and "exactly zero" means the bit pattern, not "small". A matrix zeroed by arithmetic rather than by construction will usually fail. The description says so where it will be read.
WHY THE PREDICATE IS A LIST OF ENTRIES. Every test in this family (this block, IsSymmetric and IsHermitian) reduces to a list of exact constraints assembled once and then spelt in each language's operators, which is what keeps the ten backends agreeing about WHICH entries are checked -- the one thing an i/j slip would change invisibly.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 1 |
| 0.4 | 0.5 | 1 |
| 0.8 | -2 | 1 |
| 1.2 | 0.5 | 1 |
| 1.6 | -2 | 1 |
| 2 | 0.5 | 1 |
| 2.4 | -2 | 1 |
| 2.8 | 0.5 | 1 |
| 3.2 | -2 | 1 |
| 3.6 | 0.5 | 1 |
| 4 | -2 | 1 |
| 4.4 | 0.5 | 1 |
| 4.8 | -2 | 1 |
| 5.2 | 0.5 | 1 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 1 … 1 |
ramp | Ramp: slope 1 from t = 0 | 1 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 1 … 1 |
step | Step: 0 -> 1 at t = 1 s | 1 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Matrix_Operations__IsTriangular.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).