Create Diagonal Matrix — Control Systems/Matrix Operations
Control_Systems/Matrix_Operations/Create_Diagonal_Matrix · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Create Diagonal Matrix
Control Systems / Matrix Operations
Spreads a vector onto the main diagonal of a square matrix:
y(k,k) = u(k) with every off-diagonal entry zero. This is MATLAB's
diag applied to a vector, so an n-element input gives an
[n,n] output.
A row and a column are the same input. Simulink carries a vector with no orientation and returns the same matrix either way; an ICore signal is always two-dimensional, so both [n,1] and [1,n] are accepted here and read in element order. A genuine [m,n] with both sides above one is not a vector and is reported rather than guessed at.
Ports
- u – the vector to spread: [n,1] or [1,n], of any length n. A scalar is the n = 1 case and gives a 1×1 output.
- Output – y, the [n,n] matrix carrying u on its main diagonal. Its size follows the input's LENGTH, so this block always widens a signal into a square one.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing is exposed as a tunable parameter: which entry lands where is structural and is fixed into the generated code at export time. Every target writes the off-diagonal zeros out explicitly rather than relying on the output signal being zero-initialized – a core whose signal storage is reused between steps would otherwise carry a stale value through. The three HDL targets are fully synthesizable: placing entries is a rewiring, so the cores carry plain assignments and constants with no arithmetic.
Simulink bridge
Import and export, mapped to
simulink/Matrix Operations/Create Diagonal Matrix. Nothing crosses but
the block itself: the Simulink block is a masked S-Function that defines
no dialog parameters at all, not even SampleTime, so the
entry sets hasSampleTimeParam = false and "Sampling Time (s)" stays
on the ICore side. Writing that parameter anyway would be a hard
set_param error in MATLAB rather than a warning, aborting the whole
generated script.
Notes
- Algebraic, with no state: the output depends only on the current input.
- To go the other way – a matrix's diagonal out as a vector – use Extract Diagonal.
- No state space, deliberately. The output is a MATRIX built from a vector, which no left multiplication y = D·u of the signal can produce, so model reduction reports the block as unmergeable rather than merging a matrix that does not represent it.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Matrix_Operations/Create_Diagonal_Matrix |
| family | Control_Systems/Matrix_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Create_Diagonal_Matrix |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Create_Diagonal_Matrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Create_Diagonal_Matrix.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Create_Diagonal_Matrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Create_Diagonal_Matrix.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Matrix Operations/Create Diagonal Matrix |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the rate does not cross: Simulink's Create Diagonal Matrix is a masked S-Function that defines no dialog parameters at all, so "Sampling Time (s)" stays on the ICore side. A row and a column input give the same square output on both sides.
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Create Diagonal Matrix block -- y = diag(u), a vector spread onto a diagonal MATLAB's diag() applied to a VECTOR: an n-element input becomes the [n,n] matrix with u on the main diagonal and zeros everywhere else.
A ROW AND A COLUMN ARE THE SAME INPUT. Simulink carries a vector as a 1-D signal with no orientation at all, so both come back as the same [n,n] -- confirmed against the real block, which returns diag([2 -3 0.5]) for the row and the column alike. An ICore signal is always two-dimensional, so this block accepts [n,1] and [1,n] and reads them in element order. A genuine [m,n] with both sides above one is not a vector and is reported rather than guessed at.
THE MIRROR OF Extract Diagonal, which goes the other way. MATLAB's diag() chooses between the two meanings by looking at its argument's shape; Simulink splits them into two blocks, and so does ICore -- which is what makes each one's size rule fixed instead of depending on what happens to arrive.
NO STATE SPACE, deliberately -- see the header.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Matrix_Operations__Create_Diagonal_Matrix.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).