Create 3x3 Matrix — Control Systems/Matrix Operations
Control_Systems/Matrix_Operations/Create_3x3_Matrix · 0 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Create 3x3 Matrix
Control Systems / Matrix Operations
Assembles nine scalar signals into one 3×3 matrix, row by row:
- A = [a₁₁ a₁₂ a₁₃ ; a₂₁ a₂₂ a₂₃ ; a₃₁ a₃₂ a₃₃]
The first three inputs are the first ROW, not the first column. That is measured against the Aerospace Blockset block rather than assumed: the two conventions agree on the diagonal and on any symmetric matrix, so a symmetric test cannot tell them apart.
There is no arithmetic here at all – the block copies – which is why it is the one member of its family with no rounding to describe.
Ports
- a11, a12, a13 – the first row, left to right. Each is a [1,1] scalar.
- a21, a22, a23 – the second row.
- a31, a32, a33 – the third row.
- A – the assembled matrix, [3,3].
Every input is a scalar. A port carrying a matrix is refused with the size it actually had, rather than being flattened into somewhere plausible.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing is exposed as a tunable parameter, because the block has no parameter at all – the nine entries arrive on ports.
The three HDL targets are synthesizable and bit-exact, which its three siblings are not: each generated core moves the Q16.16 word from an input port to an output element without converting it, so nothing is rounded and nothing can saturate that was not already saturated at the port. There is no multiply anywhere, so there is no range caveat either.
Simulink bridge
Both directions, onto aerolibutil/Create 3x3 Matrix in
the Aerospace Blockset. The block has no configuration, so no parameter
pairs cross.
Unlike its three siblings this path carries no embedded newline –
the Simulink block's name is drawn on one line – so it is written plainly.
The block defines no SampleTime parameter, so the rate stays
on the ICore side and a block configured with an explicit positive rate reports
that the rate did not cross.
Notes
- Algebraic and stateless: the output depends only on the current inputs, so the block cannot break an algebraic loop.
- Deliberately no state space. The map is linear, but a state space carries one input vector and this block has nine separate scalar ports, so any D matrix would have to invent a stacking order the block does not otherwise have. Model reduction therefore reports it as unmergeable.
- The nine ports are read independently every sample; nothing is held between samples, so an input that stops changing simply keeps its value in the output.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Matrix_Operations/Create_3x3_Matrix |
| family | Control_Systems/Matrix_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Create_3x3_Matrix |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Create_3x3_Matrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Create_3x3_Matrix.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Matrix_Operations/Create_3x3_Matrix/ICoreBlock_0_Control_Systems_1_Matrix_Operations_2_Create_3x3_Matrix.h |
| default size on canvas | 112 × 160 px |
| ports at insert | ? in, ? out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | a11 |
| 2 | in | ICoreDouble | a12 |
| 3 | in | ICoreDouble | a13 |
| 4 | in | ICoreDouble | a21 |
| 5 | in | ICoreDouble | a22 |
| 6 | in | ICoreDouble | a23 |
| 7 | in | ICoreDouble | a31 |
| 8 | in | ICoreDouble | a32 |
| 9 | in | ICoreDouble | a33 |
| 10 | out | ICoreDouble | A |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | aerolibutil/Create 3x3 Matrix |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the Aerospace Blockset block is a masked subsystem with no dialog parameters, so nothing but the nine signals crosses. The nine ports fill the matrix ROW BY ROW, measured on the constants 1..9. Note it defines no SampleTime parameter: an ICore rate set explicitly stays on this side and is reported
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Create 3x3 Matrix -- nine scalars in, one [3,3] out, ROW BY ROW Nine [1,1] inputs, one [3,3] output, and no arithmetic: the block copies.
MEASURED against aerolibutil/Create 3x3 Matrix (R2026a, 2026-09-10). Driving the nine ports with the constants 1..9 in port order produces
[1 2 3] [4 5 6] [7 8 9]
so the fill is ROW MAJOR and column-major is ruled out. The two orders agree on the diagonal and on any symmetric matrix, which is exactly why this was probed rather than inferred: half the obvious test matrices cannot tell them apart.
⚠ THE ONE BLOCK OF ITS FAMILY WHOSE HDL IS BIT-EXACT. Its three siblings multiply, so they round; this one moves the Q16.16 word from an input port to an output element without ever converting it, which means the fixed-point cores agree with the reference to the bit rather than to within the low bits. There is no accumulator here and no rounding caveat to state.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 [3x3] entry 0 |
|---|---|---|---|---|
| 0 | -2 | -2 | -2 | [-2, -2, -2, -2]… |
| 0.4 | 0.5 | 0.5 | 0.5 | [0.5, 0.5, 0.5, 0.5]… |
| 0.8 | -2 | -2 | -2 | [-2, -2, -2, -2]… |
| 1.2 | 0.5 | 0.5 | 0.5 | [0.5, 0.5, 0.5, 0.5]… |
| 1.6 | -2 | -2 | -2 | [-2, -2, -2, -2]… |
| 2 | 0.5 | 0.5 | 0.5 | [0.5, 0.5, 0.5, 0.5]… |
| 2.4 | -2 | -2 | -2 | [-2, -2, -2, -2]… |
| 2.8 | 0.5 | 0.5 | 0.5 | [0.5, 0.5, 0.5, 0.5]… |
| 3.2 | -2 | -2 | -2 | [-2, -2, -2, -2]… |
| 3.6 | 0.5 | 0.5 | 0.5 | [0.5, 0.5, 0.5, 0.5]… |
| 4 | -2 | -2 | -2 | [-2, -2, -2, -2]… |
| 4.4 | 0.5 | 0.5 | 0.5 | [0.5, 0.5, 0.5, 0.5]… |
| 4.8 | -2 | -2 | -2 | [-2, -2, -2, -2]… |
| 5.2 | 0.5 | 0.5 | 0.5 | [0.5, 0.5, 0.5, 0.5]… |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 7d7903fbad81ee6be6501ad2be0e1260e9995f8f · produced by docsSample --out <folder> --blocks Determinant_Of_3x3_Matrix Adjoint_Of_3x3_Matrix Invert_3x3_Matrix Create_3x3_Matrix --steps 60 · data docs/generated/samples/Control_Systems__Matrix_Operations__Create_3x3_Matrix.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).