Lookup Table Dynamic — Control Systems/Lookup Tables
Control_Systems/Lookup_Tables/Lookup_Table_Dynamic · 3 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Lookup Table Dynamic
Control Systems / Lookup Tables
A one-dimensional lookup whose table arrives on ports rather than coming from configuration: y = table(u), with the axis on xdat and the values on ydat, both read afresh every step.
That is the whole reason to reach for it over 1-D Lookup Table: the table can be computed, scheduled or retuned while the model runs. The cost is that nothing about it can be folded into the generated code – see Code export.
Ports
- Input u – the value to look up, of any size [m,n]. Each entry is looked up independently.
- Input xdat – the axis, a vector of at least two strictly increasing values. Read every step, so it may change during the run.
- Input ydat – the table's values, a vector of the same length as xdat.
- Output – the table's value y, the SAME size as u.
Parameters
- Lookup Method – what the table says between two points, and outside
them. Simulink's five, under Simulink's own names.
- Interpolation-Extrapolation – a straight line between the two neighbours, continued past either end along the slope of the end interval.
- Interpolation-Use End Values – the same line between the points, but the end values are held outside the axis rather than extrapolated.
- Use Input Nearest – the value at the nearer point. An exact tie takes the higher one.
- Use Input Below – the value at the point at or below the input, a staircase stepping at each point.
- Use Input Above – the value at the point at or above the input, the same staircase shifted one point earlier.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing about the table is baked in – it is read from the ports every step, which is the point of the block – so only its length reaches the generated code, as the number of branches in the search.
The three HDL targets are simulation-only here. Every other table in this family folds each interval's slope into one constant at export time and so needs no divider; this one cannot know its axis until the core runs, so the two interpolating methods perform a genuine division each step. That is emitted for simulation and is not offered as synthesizable. The three staircase methods (Below, Above, Nearest) never divide, so they carry no such caveat beyond the usual Q16.16 range limit of ±32767.
Simulink bridge
Import and export, mapped to
simulink/Lookup Tables/Lookup Table Dynamic. "Lookup Method" to
LookUpMeth – the five values are Simulink's own strings, so that
mapping is 1:1 and lossless both ways. The table is not a parameter on either side;
it crosses as the two signals feeding xdat and ydat.
This Simulink block has no SampleTime parameter (verified
against the R2026a dialog), so the rate stays on the ICore side and a block
configured with an explicit positive rate reports that it did not cross.
Notes
- Algebraic, with no state – but not constant-foldable, since the table is an input.
- Elementwise over u: the output carries u's size, while xdat and ydat are vectors shared by every entry.
- Use Input Above and Use Input Nearest agree on any input sitting in the upper half of its interval. They differ only in the lower half, which is worth knowing when checking one against the other.
- Not linear, and so deliberately carries no state space.
- See 1-D Lookup Table for the same lookup with the table in configuration, which is the faster and more portable choice whenever the table is fixed.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Lookup_Tables/Lookup_Table_Dynamic |
| family | Control_Systems/Lookup_Tables |
| solver environment class | ICoreBlock_0_Control_Systems_1_Lookup_Tables_2_Lookup_Table_Dynamic |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Lookup_Tables/Lookup_Table_Dynamic/ICoreBlock_0_Control_Systems_1_Lookup_Tables_2_Lookup_Table_Dynamic.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Lookup_Tables/Lookup_Table_Dynamic/ICoreBlock_0_Control_Systems_1_Lookup_Tables_2_Lookup_Table_Dynamic.h |
| default size on canvas | 95 × 80 px |
| ports at insert | 3 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | xdat |
| 3 | in | ICoreDouble | ydat |
| 4 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Lookup Method | Interpolation-Extrapolation%~%Interpolation-Use End Value… | LookUpMeth |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Lookup Tables/Lookup Table Dynamic |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Lookup Method | LookUpMeth | Interpolation-Extrapolation → Interpolation-Extrapolation, Interpolation-Use End Values → Interpolation-Use End Values, Use Input Nearest → Use Input Nearest, Use Input Below → Use Input Below, Use Input Above → Use Input Above |
Caveat (shown to the user): the table is not a parameter on either side - it crosses as the two signals feeding xdat and ydat. This Simulink block has NO SampleTime parameter (verified against the R2026a dialog), so the rate stays on the ICore side and a block configured with an explicit positive rate reports that it did not cross
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0every stimulus in the sample errored — cross-checks skipped
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Lookup Table Dynamic — a 1-D lookup whose table arrives on ports y = table(u) axis on xdat, values on ydat, both read every step
Algebraic and stateless, elementwise over u. No state space (see header).
THE SLOPE IS A RUNTIME DIVISION, which is what sets this block apart from every other table in the family. They know their axis at export time and fold each interval's slope into one constant; this one cannot, so the two interpolating methods divide while the core runs. The seven software targets do that directly. The three HDL targets are SIMULATION-ONLY for that reason - a Q16.16 divider is not something to emit into a synthesizable core by accident - and the block's description says so rather than shipping a quietly unsynthesizable core.
THE SEARCH IS STILL UNROLLED. The table's LENGTH is fixed when the model is built even though its VALUES are not, so the chain of comparisons is emitted once per interval exactly as the config-driven tables do - only the operands are port reads instead of literals.
Sample results#
No stimulus produced a sampled output in this rig — Lookup Table Dynamic has a mis-shaped table at: ICore Blocks/Home/Lookup Table Dynamic. That is a fact about the single-block rig, not a verdict on the block: an offline batch fit, a block whose output only appears at onSolverFinish, or one that needs a driven environment cannot be exercised alone.
Category unsampled · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60
Sample data: docs/generated/samples/Control_Systems__Lookup_Tables__Lookup_Table_Dynamic.json