Interpolation Using Prelookup — Control Systems/Lookup Tables
Control_Systems/Lookup_Tables/Interpolation_Using_Prelookup · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Interpolation Using Prelookup
Control Systems / Lookup Tables
Reads a table at a position that arrived on ports rather than being searched for here: y = table(k, f), where k is an interval index and f the fraction across it – exactly the pair Prelookup publishes.
Pairing the two is the point: several tables sharing one axis search it once in a single Prelookup and read it many times here, instead of each repeating the search.
Ports
- Input k – the interval index, counted from zero, of any size [m,n]. Values at or above the table's last interval are held there, as Simulink does.
- Input f – the fraction across that interval, the SAME size as k. Under Linear extrapolation it may lie outside [0,1], which is what makes the output extrapolate.
- Output – the table's value y, the same size again.
Parameters
- Table Data – the table, as a row or column vector; both spell the same list. At least two values.
- Interpolation Method – what the table says at (k, f).
- Linear point-slope – a straight line across interval k: y = T[k] + f·(T[k+1] − T[k]).
- Flat – the entry at the position k + f, rounded down.
- Nearest – the entry nearest that position; an exact tie takes the higher one.
- Extrapolation Method – what to do with a fraction outside [0,1].
- Linear – let it through, so the straight line continues past the end of the interval.
- Clip – hold it in [0,1].
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
The two rules do not read the same input
Linear needs the interval, so it branches on k and interpolates with f inside that branch. Flat and Nearest select one entry by the position k + f, so a pair like (k = 2, f = 1) lands on entry 3 rather than entry 2 – verified against R2026a, where that pair on the table [1 3 2 5] returns 5. It matters because (k = n−2, f = 1) is exactly what a Prelookup reports at its last breakpoint.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The table and both rules are baked into the arithmetic at export time rather than exposed as tunable parameters, and they have to be: the number of entries decides how many branches the generated code has.
The three HDL targets are not simulation-only: every branch is one multiply and one add on constants known at export time, so no divider is emitted. The caveat is range – a signal is carried in Q16.16 there, so a table value outside ±32767 cannot be represented.
Simulink bridge
Import and export, mapped to
simulink/Lookup Tables/Interpolation Using Prelookup. "Table Data" to
Table, "Interpolation Method" to InterpMethod and
"Extrapolation Method" to ExtrapMethod – those values are
Simulink's own strings, so the mappings are 1:1 and lossless both ways. The block
always writes NumberOfTableDimensions = 1.
Simulink's block generalizes to n dimensions, taking an index and a fraction
per dimension (four input ports for a 2-D table, six for a 3-D one). This block is
one-dimensional, so a model importing a multi-dimensional one is reported
rather than silently flattened. Simulink's Linear Lagrange method likewise has
no counterpart here. "Sampling Time (s)" goes to SampleTime, as on every
block.
Notes
- Algebraic, with no state.
- Elementwise: the output carries the inputs' size, and each entry is read on its own. Both inputs must be the same size.
- Not linear, and so deliberately carries no state space.
- See Prelookup for the block that produces (k, f), and 1-D Lookup Table for both halves in one block.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Lookup_Tables/Interpolation_Using_Prelookup |
| family | Control_Systems/Lookup_Tables |
| solver environment class | ICoreBlock_0_Control_Systems_1_Lookup_Tables_2_Interpolation_Using_Prelookup |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Lookup_Tables/Interpolation_Using_Prelookup/ICoreBlock_0_Control_Systems_1_Lookup_Tables_2_Interpolation_Using_Prelookup.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Lookup_Tables/Interpolation_Using_Prelookup/ICoreBlock_0_Control_Systems_1_Lookup_Tables_2_Interpolation_Using_Prelookup.h |
| default size on canvas | 95 × 70 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | k |
| 2 | in | ICoreDouble | f |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Table Data | [0 0.5 1.5 3 5] | Table |
Interpolation Method | LUT::interpComboSpec() | InterpMethod |
Extrapolation Method | LUT::extrapComboSpec() | ExtrapMethod |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Lookup Tables/Interpolation Using Prelookup |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | NumberOfTableDimensions = 1 |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Table Data | Table | passes through |
Interpolation Method | InterpMethod | Flat → Flat, Nearest → Nearest, Linear point-slope → Linear point-slope |
Extrapolation Method | ExtrapMethod | Clip → Clip, Linear → Linear |
Caveat (shown to the user): one-dimensional: Simulink's block generalizes to n dimensions, taking an index and a fraction per dimension (four input ports for a 2-D table), so a model importing a multi-dimensional one is reported rather than silently flattened. Simulink's Linear Lagrange method has no counterpart here either. Note that Flat and Nearest ignore the extrapolation method on BOTH sides, and that they select on the POSITION k+f while Linear branches on k alone
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Interpolation Using Prelookup — read a table at a position that arrived on ports y = table(k, f) (k, f) being what a Prelookup published for some axis
Algebraic and stateless, elementwise. One dimension; no state space (see header).
THE CLAMP IS EMITTED ONLY FOR Linear. Flat and Nearest ignore the extrapolation rule on both sides, so clamping the fraction for them would change answers Simulink does not change.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|---|
| 0 | -2 | -2 | -1 |
| 0.4 | 0.5 | 0.5 | 1 |
| 0.8 | -2 | -2 | -1 |
| 1.2 | 0.5 | 0.5 | 1 |
| 1.6 | -2 | -2 | -1 |
| 2 | 0.5 | 0.5 | 1 |
| 2.4 | -2 | -2 | -1 |
| 2.8 | 0.5 | 0.5 | 1 |
| 3.2 | -2 | -2 | -1 |
| 3.6 | 0.5 | 0.5 | 1 |
| 4 | -2 | -2 | -1 |
| 4.4 | 0.5 | 0.5 | 1 |
| 4.8 | -2 | -2 | -1 |
| 5.2 | 0.5 | 0.5 | 1 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1.5 |
ramp | Ramp: slope 1 from t = 0 | 0 … 14.6 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.5 … 1.5 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1.5 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Lookup_Tables__Interpolation_Using_Prelookup.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).