Direct Lookup Table nD — Control Systems/Lookup Tables
Control_Systems/Lookup_Tables/Direct_Lookup_Table_nD · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Direct Lookup Table (n-D)
Control Systems / Lookup Tables
Selects one entry of a table by index: y = table[i1][i2]. There is no axis and nothing is ever blended – the inputs are the position, which is what separates this block from every other table in the family.
Reach for it when the position is already known as a whole number: a mode, a gear, a state, a bin. When the position is a physical quantity that has to be located on an axis, use 2-D Lookup Table instead.
Ports
- Input i1 – the row index, a scalar, counted from zero.
- Input i2 – the column index, a scalar, counted from zero.
- Output – the selected entry y, a scalar.
Parameters
- Table Data – the table, any matrix of at least one row and one column. It is the only parameter: with no axis there is nothing else to configure.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
The index is floored, not rounded
An index of 1.6 selects entry 1, not entry 2, and 0.6 selects entry 0. An index outside the table is held at the nearer end, so a negative index reads the first entry and an index past the end reads the last. This is Simulink's behaviour (verified against the R2026a block with the table [4 5 6 7], where 0.6, 1.6, 2.5 and 3.6 return 4, 5, 6 and 7, and −1.6 returns 4) rather than a choice made here. Reading it as "round to the nearest entry" is wrong on every fractional index.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The table is baked in at export time rather than exposed as a tunable parameter: its shape decides how many branches the generated code has, so the table and the structure of the code cannot be separated.
The three HDL targets are not simulation-only, and this is the cheapest
block in the family for them: the flooring and clamping fall out of the comparison
chain itself, so no floor(), no min/max and no arithmetic of any kind is
emitted – only comparisons and constant assignments. The caveat is range
– a signal is carried in Q16.16 there, so a table value outside ±32767
cannot be represented.
Simulink bridge
Import and export, mapped to
simulink/Lookup Tables/Direct Lookup Table (n-D). "Table Data" to
Table as a plain pass-through value, so the round trip is lossless. The
block always writes NumberOfTableDimensions = 2 and
InputsSelectThisObjectFromTable = Element, which is what two index
ports and a scalar output mean. "Sampling Time (s)" goes to SampleTime,
as on every block.
Simulink's block generalizes to n dimensions, taking one index port per
dimension, and can also return a whole Vector or 2-D Matrix slice
instead of a single element. Neither has a counterpart here, so a model importing one
is reported rather than silently reshaped. Simulink also defaults its
out-of-range diagnostic to Warning; this block always writes
None, since holding at the nearer end is the defined behaviour on both sides
and a warning per step would flood the run log.
Notes
- Algebraic, with no state.
- Not linear, and so deliberately carries no state space – selecting a table entry is not a linear map in any useful sense.
- See 2-D Lookup Table for the same table read through two axes with interpolation.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Lookup_Tables/Direct_Lookup_Table_nD |
| family | Control_Systems/Lookup_Tables |
| solver environment class | ICoreBlock_0_Control_Systems_1_Lookup_Tables_2_Direct_Lookup_Table_nD |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Lookup_Tables/Direct_Lookup_Table_nD/ICoreBlock_0_Control_Systems_1_Lookup_Tables_2_Direct_Lookup_Table_nD.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Lookup_Tables/Direct_Lookup_Table_nD/ICoreBlock_0_Control_Systems_1_Lookup_Tables_2_Direct_Lookup_Table_nD.h |
| default size on canvas | 85 × 75 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | i1 |
| 2 | in | ICoreDouble | i2 |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Table Data | [4 5 6; 16 19 20; 10 18 23] | Table |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Lookup Tables/Direct Lookup Table (n-D) |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | NumberOfTableDimensions = 2, InputsSelectThisObjectFromTable = Element, DiagnosticForOutOfRangeInput = None |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Table Data | Table | passes through |
Caveat (shown to the user): two-dimensional and element-selecting: Simulink's block generalizes to n dimensions (one index port each) and can return a Vector or 2-D Matrix slice instead of a single element, so a model importing either is reported rather than silently reshaped. The index is FLOORED and counted from zero on both sides, and held at the nearer end when out of range - which is why the out-of-range diagnostic is written as None rather than Simulink's default Warning, a warning per step being a flooded run log for behaviour that is defined
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Direct Lookup Table (n-D) — select one table entry by index y = table[i1][i2] no axis, no interpolation, no extrapolation
Algebraic, stateless, scalar in and out, two dimensions. No state space (see header).
THE INDEX IS FLOORED AND CLAMPED, which the emitted chain gets for free: a branch on "index < j+1" taken in order selects entry j for anything in [j, j+1), sends everything below 1 (negatives included) to entry 0, and falls through to the last entry. That IS floor-then-clamp, spelled as comparisons - so no target needs a floor() or a min/max, and the three HDL backends stay ordinary comparison logic.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|---|
| 0 | -2 | -2 | 4 |
| 0.4 | 0.5 | 0.5 | 4 |
| 0.8 | -2 | -2 | 4 |
| 1.2 | 0.5 | 0.5 | 4 |
| 1.6 | -2 | -2 | 4 |
| 2 | 0.5 | 0.5 | 4 |
| 2.4 | -2 | -2 | 4 |
| 2.8 | 0.5 | 0.5 | 4 |
| 3.2 | -2 | -2 | 4 |
| 3.6 | 0.5 | 0.5 | 4 |
| 4 | -2 | -2 | 4 |
| 4.4 | 0.5 | 0.5 | 4 |
| 4.8 | -2 | -2 | 4 |
| 5.2 | 0.5 | 0.5 | 4 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 4 … 19 |
ramp | Ramp: slope 1 from t = 0 | 4 … 23 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 4 … 4 |
step | Step: 0 -> 1 at t = 1 s | 4 … 19 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Lookup_Tables__Direct_Lookup_Table_nD.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).