Logical Operator — Control Systems/Logic And Bit Operations
Control_Systems/Logic_And_Bit_Operations/Logical_Operator · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Logical Operator
Control Systems / Logic and Bit Operations
Combines boolean signals: AND, OR, NAND, NOR, XOR and NXOR over as many inputs as you give it, or NOT over one. The work is done entry by entry, so two [2,3] signals produce a [2,3] answer.
Ports
- Inputs (
bool) – two by default, and the count is user-editable. Every input carries the boolean typeICoreBooland nothing else. They must all be the same size [m,n], or be scalars, which are then combined with every entry of the others. NOT takes exactly one input; the other six take at least two. - Output (
bool) – the result, of the inputs' shared size [m,n], carryingICoreBool.
Feeding it a number
This block accepts boolean signals only. A link joins two ports of the same type or is refused, so a floating-point or integer signal reaches this block through a Data Type Conversion block set to boolean – which puts the "treat non-zero as true" step on the canvas where you can see it. Simulink's version of this block reinterprets a double silently; this one asks you to say so.
Parameters
- Operator – which combination is taken. This selects the
operation rather than retuning it, so each option is a separate code path.
- AND – true when every input is true. The default, as in Simulink.
- OR – true when any input is true.
- NAND – the negation of AND.
- NOR – the negation of OR.
- XOR – true when an ODD number of inputs is true, which is what chaining exclusive-or across several inputs means.
- NXOR – the negation of XOR, so true when an EVEN number of inputs is true.
- NOT – the negation of a single input.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets carry this block – Python, MATLAB, Java, Rust, C, C++, PLC Structured Text, VHDL, Verilog and SystemVerilog. The operator is fixed into the generated code at export time, so there is nothing left to retune on the generated core.
The three HDL targets carry every signal in one fixed-point format
(Q16.16), so each input is tested against zero rather than read as a single bit,
and the result is written back as 1.0 or 0.0 in that format. The output port is
ICoreBool, so the write-time quantize applies to it as well –
which is what keeps the stored value a true boolean rather than whatever the
arithmetic left behind.
Simulink bridge
Import and export, mapped to simulink/Logic and Bit Operations/Logical
Operator. "Operator" to Operator, one option for one option
(AND, OR, NAND, NOR,
XOR, NXOR, NOT), so that round trip is
lossless; the input port count becomes Simulink's Inputs number and
an imported count becomes this port list; "Sampling Time (s)" to
SampleTime, as on every block.
OutDataTypeStr is always written as boolean,
because this block's output is boolean whatever arrives and has no choice to
offer. IconShape is a drawing choice with no counterpart here and
does not cross.
Notes
- Algebraic, with no state: the output depends only on the current inputs.
- Not linear – there is no A/B/C/D that expresses "non-zero" – so the block deliberately carries no state space and model reduction reports it as unmergeable.
- The block itself never rounds or clamps. It produces 1 or 0 and the output port applies the boolean type once, which is what makes the simulation and the generated code agree exactly rather than approximately.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Logic_And_Bit_Operations/Logical_Operator |
| family | Control_Systems/Logic_And_Bit_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Logical_Operator |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Logical_Operator/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Logical_Operator.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Logical_Operator/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Logical_Operator.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreBool | — |
| 2 | in | ICoreBool | — |
| 3 | out | ICoreBool | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Operator | AND%~%OR%~%NAND%~%NOR%~%XOR%~%NXOR%~%NOT~~AND | Operator |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Logic and Bit Operations/Logical Operator |
| port-count rule | PortsParam::LogicalOperatorInputs |
SampleTime parameter | yes |
| always set | OutDataTypeStr = boolean |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Operator | Operator | AND → AND, OR → OR, NAND → NAND, NOR → NOR, XOR → XOR, NXOR → NXOR, NOT → NOT |
Caveat (shown to the user): the seven operators map 1:1 onto Simulink's, so the choice is lossless in both directions; this block's inputs are ICoreBool and nothing else, where Simulink's reinterprets a double as non-zero, so a double-driven Simulink model imports with the conversion left for the user to place
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Logical Operator -- AND, OR, NAND, NOR, XOR, NXOR over N inputs, or NOT over one The first block in the library whose ports carry the BOOLEAN signal type on both sides, and therefore the first one for which a library preview, a link, a test rig and an exported core all have to agree about a type that is not a 64-bit float.
ONE RULE, SPELLED ONCE. The seven operators are seven code paths, but every generator builds the same expression through one shared helper in this file: each input becomes a "is it non-zero" term in that language's spelling, the terms are folded together with that language's AND / OR / XOR token, and the negated operators wrap the result in that language's NOT. Writing seven operators x seven languages out by hand would be dozens of places for one of them to drift; this is one rule, spelled once per language.
THE BLOCK NEVER ROUNDS ITS OWN OUTPUT. It returns 1.0 or 0.0 as plain numbers and the OUTPUT PORT applies the boolean type when it stores them -- once, in the simulator, and once in every generated core. Which is also why the truth test is "is it non-zero" everywhere and not "is it above a half": it is the port's own rule, quoted rather than re-invented.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.