Interval Test Dynamic — Control Systems/Logic And Bit Operations
Control_Systems/Logic_And_Bit_Operations/Interval_Test_Dynamic · 3 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Interval Test Dynamic
Control Systems / Logic And Bit Operations
Answers 1 where an entry of the signal lies inside an interval and 0 where it does not, with both ends of the interval arriving on ports rather than coming from config: y = (u ≥ lo) ∧ (u ≤ up), with each end independently made open instead. The comparison is applied entry by entry, so the signal's size is unchanged.
Ports
- up – the upper limit, and the FIRST input port, which is Simulink's own order. Either the same size [m,n] as u or a scalar broadcast over every entry of it.
- u – the signal being tested, of any size [m,n], and the second input port. Its size is the block's output size.
- lo – the lower limit, and the LAST input port. Same size rule as up.
- Output – y, of the SAME size [m,n] as u. Every entry is 1 or 0. It is carried as an ordinary real signal, not a boolean type – every port in this library is a real matrix – so it can be fed straight into arithmetic as a 0/1 mask.
Parameters
- Lower Bound – whether lo itself counts as inside.
- Closed (u >= lo) – it does. The default, as in Simulink.
- Open (u > lo) – it does not.
- Upper Bound – the same choice at the other end.
- Closed (u <= up) – up counts as inside. The default, as in Simulink.
- Open (u < up) – it does not.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. Nothing numeric is baked in – both limits are
signals and are read from their ports every step – so the only export-time
choice is which comparison operators the two bound kinds spell. The three HDL
targets are fully synthesizable: two signed compares and a conjunction, with no
arithmetic, so nothing is evaluated in real.
Simulink bridge
Import and export, mapped to simulink/Logic and Bit Operations/Interval
Test Dynamic. "Lower Bound" to IntervalClosedLeft and "Upper
Bound" to IntervalClosedRight, each with its two options mapped
onto on and off, so both round trip losslessly.
OutDataTypeStr is always written as boolean: this
block has no data-type choice to offer, and pinning it is what keeps the two
sides comparing the same thing. The three input ports are in Simulink's own
order – up, u, lo – so a wire crosses onto the
port it came from.
The Simulink block defines no SampleTime parameter, so
"Sampling Time (s)" does not cross – a block left at the inheriting
default loses nothing, and one given an explicit period is reported rather than
silently dropped.
Notes
- Algebraic, with no state: the output depends only on the current inputs.
- Not linear – the output is a two-valued step function of its inputs – so the block deliberately carries no state space and model reduction reports it as unmergeable.
- The upper limit is the first port and the lower limit is the last. That is Simulink's order, and it is the opposite of what the block's name suggests; the ports carry the names up, u and lo on the block face for exactly that reason.
- Nothing checks that lo stays at or below up: they are signals, and either could cross the other for a few samples in a working model. Where they do cross the interval is empty and the output is 0, which is the same answer Simulink gives.
- An HDL core sees all three inputs already quantized to one part in 1.5×10⁻⁵, so an entry within one quantum of either limit can land on the other side of it. The open/closed distinction is exactly one quantum wide there.
- For limits that are fixed rather than wired, use Interval Test, which takes them as config and inlines them at export.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Logic_And_Bit_Operations/Interval_Test_Dynamic |
| family | Control_Systems/Logic_And_Bit_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Interval_Test_Dynamic |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Interval_Test_Dynamic/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Interval_Test_Dynamic.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Interval_Test_Dynamic/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Interval_Test_Dynamic.h |
| default size on canvas | 90 × 90 px |
| ports at insert | 3 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | up |
| 2 | in | ICoreDouble | u |
| 3 | in | ICoreDouble | lo |
| 4 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Lower Bound | Closed (u >= lo)%~%Open (u > lo)~~Closed (u >= lo) | IntervalClosedLeft |
Upper Bound | Closed (u <= up)%~%Open (u < up)~~Closed (u <= up) | IntervalClosedRight |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Logic and Bit Operations/Interval Test Dynamic |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | OutDataTypeStr = boolean |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Lower Bound | IntervalClosedLeft | Closed (u >= lo) → on, Open (u > lo) → off |
Upper Bound | IntervalClosedRight | Closed (u <= up) → on, Open (u < up) → off |
Caveat (shown to the user): both parameters map 1:1 onto the Simulink block's, so the choice is lossless in both directions; the three input ports are in Simulink's own order (up, u, lo -- the UPPER limit first); the Simulink block has NO SampleTime parameter, so "Sampling Time (s)" does not cross
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Interval Test Dynamic block -- is each entry inside an interval that ARRIVES ON PORTS? y = 1 where lo <(=) u <(=) up holds and y = 0 where it does not, with lo and up read from input ports rather than from config. Each END is still independently CLOSED (the limit itself counts as inside) or OPEN, because that is a structural choice rather than a numeric one and Simulink keeps it a parameter too.
⚠ THE PORT ORDER IS UP, U, LO -- MEASURED, NOT GUESSED. R2026a's masked subsystem holds three Inports and their numbers were read off it directly:
Inport #1 "up" Inport #2 "u" Inport #3 "lo"
The upper limit is FIRST and the lower limit is LAST, which is the opposite of the order the block's own name suggests. This block creates its ports in that same order and labels them with those names, so the bridge's add_line indices line up and a reader of the block face cannot invert the interval by accident.
A limit port may carry u's size or be a SCALAR broadcast over it, exactly as Math Function's second operand may. The output always carries u's size.
The output is a REAL signal carrying 1.0 and 0.0, not a boolean type -- every port in this library is ICoreDouble. Simulink's counterpart emits a
boolean, which logs as 1/0, so the two agree numerically; the bridge pins OutDataTypeStr to boolean so that stays true.Code export: the two bound kinds are structural and are emitted as the comparison operators themselves. NOTHING numeric is inlined -- both limits are signals, so every target reads them from their ports each step.
HDL: fully synthesizable. Two signed compares and an AND, no arithmetic, so the three HDL cores stay in the fixed-point datapath. Both limits arrive ALREADY QUANTIZED here rather than being rounded once at export, which is the caveat in the description.
Algebraic and stateless. No state space -- see the header.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.