Integer To Bit Converter — Control Systems/Logic And Bit Operations

Integer to Bit Converter

Control Systems / Logic And Bit Operations

Unpacks every entry of the input into n separate entries carrying 0 or 1, where n is Number of Bits. At 3 bits, most significant first, 5 becomes [1 0 1]. A negative value is written in two's complement over the same width: at 4 bits, -8 becomes [1 0 0 0] and -1 becomes [1 1 1 1].

Each entry's bits sit contiguously in that entry's own place, so an input of w entries gives an output of w×n entries. The value unpacked is the entry rounded to the nearest whole number and reduced modulo 2ⁿ, which is what makes the block total on a wire that carries doubles – see Notes.

Ports

• Input – the signal u whose entries are unpacked. A vector: [m,1], [1,n] or a scalar. A matrix with both dimensions above one is reported rather than flattened, because which way it would be flattened is exactly the question a user would be guessing at.
• Output – y, the bits. Its size follows the input's: a column of w entries gives a column of w×n, a row gives a row of w×n, and a scalar gives a column of n.

Parameters

• Number of Bits – how many bits each entry becomes. A whole number from 1 to 32; the default is 3, which is the Simulink block's default too.
• Bit Order – which end of the word comes out first.
  • MSB first – the most significant bit is the first of each entry's n outputs. The default.
  • LSB first – the least significant bit comes first; the same word, reversed.
• Input Signedness – whether the input is meant to carry signed values. It changes no emitted bit, and that is arithmetic rather than an omission: the two's-complement pattern of a negative value and the unsigned residue of that value modulo 2ⁿ are the same pattern, so at 4 bits both -1 and 15 give [1 1 1 1]. The setting declares what the input means and is carried so that it survives a round trip through Simulink.
  • Unsigned – entries are meant to lie in 0, 2ⁿ). The default.
  • Signed – entries are meant to lie in [-2^n-1, 2^n-1).
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The bit count, the order and the whole unpacking are resolved at export time and inlined, so a generated core carries a fixed list of assignments with no loop and no index arithmetic; none of the three is a tunable parameter on the exported core.

The seven software targets compute the residue with floor only – never a remainder operator, whose sign convention differs between languages on exactly the negative inputs this block is most often given – so all seven are bit-identical. PLC Structured Text has no FLOOR and its TRUNC rounds toward zero, so the floor is rebuilt from TRUNC with the standard sign correction.

The three HDL targets are genuine synthesizable Q16.16: the round is one add and one arithmetic shift (fx_to_int), and the rest is integer division by constants. Their fixed-point format holds whole numbers up to about ±32768, so a word wider than 15 bits unsigned (16 signed) exceeds what a fixed-point port can represent and those three columns will not match; the seven software targets are exact to the full 32.

Simulink bridge

Import and export, mapped to simulink/Logic and Bit Operations/Integer to Bit Converter. Number of Bits → nbits, Bit Order → bitOrder and Input Signedness → signedInputValues, each 1:1 and therefore lossless both ways. Simulink's outDtype selects the integer TYPE of the emitted bits and has no counterpart here, every ICore signal being a matrix of doubles, so it is left at its Simulink default.

The rate does NOT cross. That block defines no SampleTime parameter – verified by set_param against R2026a, which answers "Integer to Bit Converter block (mask) does not have a parameter named 'SampleTime'" – so "Sampling Time (s)" stays on the ICore side. Writing it anyway would be a hard error that aborts the whole generated script rather than a warning that degrades.

Notes

• Algebraic, with no state: the output depends only on the current input.
• The block is total, where Simulink's is not. Simulink's counterpart takes an integer-typed input, so it can refuse anything else, and it does – a non-integer or out-of-range value STOPS the simulation with "Inputs must be integers in the range 0 to (2^(BitsPerInteger) - 1)". An ICore wire carries doubles and has no type to refuse with, so this block defines the value instead: the entry is rounded with floor(v + ½) and reduced modulo 2ⁿ. The two agree exactly on every input Simulink accepts; where they differ, Simulink gives no answer at all rather than a different one.
• The output is a different SIZE from the input, and it is fixed for the run. A downstream block that requires its inputs to agree in size must be given signals that do.
• No state space, deliberately. The map is a rounding and a modulus, so it is not linear, and its output is a different size from its input; carrying one would offer the block for model-reduction merges it cannot serve.
• To go the other way – a group of bits back into one number – use Bit to Integer Converter, whose parameters are the mirror of these.