Extract Bits — Control Systems/Logic And Bit Operations

Extract Bits

Control Systems / Logic And Bit Operations

Reads its input as a whole number held in a word of W bits and answers a contiguous field of n of those bits, taken from bit low upwards: y = (floor(u) mod 2^W ÷ 2^low) mod 2ⁿ, optionally multiplied by 2^low to leave the field at its original weight. Bit 0 is the LEAST significant bit. Applied entry by entry, so a matrix signal is treated element for element and the signal's size is unchanged.

Ports

• Input – the word u, of any size [m,n]. It is read as a whole number: the fractional part is discarded by floor, and a value outside [0, 2^W) is wrapped into that range, which is what a negative input does.
• Output – y, of the SAME size [m,n] as the input, carrying the extracted field as an ordinary real signal.

Parameters

• Bits to Extract – which field is taken. This selects the field rather than retuning it, so each option is a separate code path.
  • Upper half – the top half of the word: low = W÷2 rounded DOWN, n = W − W÷2. The default, as in Simulink.
  • Lower half – the bottom half: low = 0, and the same width as the upper half. On an ODD word that means the two halves are each (W+1)÷2 bits and they OVERLAP on the middle bit – measured, not rounded away.
  • Range starting with most significant bit – the top Number of Bits bits: low = W − Number of Bits. A count larger than the word makes low negative, which shifts the whole word UP rather than being an error.
  • Range ending with least significant bit – the bottom Number of Bits bits: low = 0, n = Number of Bits.
  • Range of bits – the field named by Bit Index Range.
• Number of Bits – a positive whole number, read only by the two Range … with … bit options. Defaults to 8, as in Simulink.
• Bit Index Range – a two-entry vector [low high], read only by Range of bits. Both ends are INCLUSIVE and indices count from bit 0 at the least significant end, so [3 9] is a seven-bit field. Defaults to [0 7], as in Simulink. A reversed pair gives a one-bit field at low, which is what Simulink answers.
• Output Scaling Mode – what weight the extracted field carries.
  • Preserve fixed-point scaling – the field keeps its place in the word, i.e. the answer is multiplied by 2^low. The default, as in Simulink.
  • Treat bit field as an integer – the field is brought down to bit 0.
• Input Word Length (bits) – W, a whole number from 1 to 53. This block has no data types, so the word length is a parameter here where in Simulink it is the width of the input signal's integer type; it decides where the halves fall, what a range off the top reads and where a negative input wraps to. Defaults to 16.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every choice is structural and is baked into the generated body at export time rather than exposed as a tunable parameter: the field is emitted as the two exact powers of two that shift and mask it. The four whole-number targets carry a narrower word than the other six. The three HDL cores turn the input into a whole number with a 32-bit integer and hand the answer back through a Q16.16 port, and PLC Structured Text builds its floor from TRUNC, which yields a DINT – so a word longer than 30 bits, or a configuration whose largest possible output exceeds 32767, is refused by those four with a message naming the limit, rather than exported as something that silently overflows. The seven software targets carry the block to the full 53 bits.

Simulink bridge

Import and export, mapped to simulink/Logic and Bit Operations/Extract Bits. "Bits to Extract" to bitsToExtract and "Output Scaling Mode" to outScalingMode, one option for one option, so both round trips are lossless; "Number of Bits" to numBits and "Bit Index Range" to bitIdxRange as plain pass-through values. "Input Word Length (bits)" does NOT cross and is reported: on the Simulink side that number is the width of the INPUT SIGNAL's integer data type, not a parameter of the block, so no set_param can carry it – a model crossing either way needs a Data Type Conversion of the matching width in front of the block.

The Simulink block defines no SampleTime parameter, so "Sampling Time (s)" does not cross – a block left at the inheriting default loses nothing, and one given an explicit period is reported rather than silently dropped.

Notes

• Algebraic, with no state: the output depends only on the current input.
• Not linear – floor, a wrap and a mask are not a linear map – so the block deliberately carries no state space and model reduction reports it as unmergeable.
• The input is read with floor, not rounding, which is the same direction the HDL targets' fx_to_int takes and is what keeps the ten backends agreeing on a value that is not already whole. Feed the block whole numbers if the distinction matters.
• A field that runs off the top of the word reads zeros there rather than raising an error, and a Range starting with most significant bit whose count exceeds the word shifts the word UP instead. Both are what Simulink answers, measured.
• On an odd word the two halves overlap on the middle bit, because each of them is (W+1)÷2 bits wide rather than one being the remainder of the other. Measured against Simulink on a 5-bit word.
• Simulink's counterpart is a pass-through on a floating-point signal – it reads a stored integer – so a model crossing the bridge needs a Data Type Conversion to the matching integer type in front of it. This block reads its own input as a whole number instead, which is what lets it stand in an all-real signal path.
• To extract the exponent, mantissa or sign of a floating-point value rather than a field of an integer word, that is a different block – this one reads its input as a whole number.