Detect Change — Control Systems/Logic And Bit Operations
Control_Systems/Logic_And_Bit_Operations/Detect_Change · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Detect Change
Control Systems / Logic And Bit Operations
Reports, as a 1.0/0.0 flag, whether the input differs from the previous sample in either direction:
y[k] = 1 when u[k] ≠ u[k−1], and 0 when the sample is unchanged
Applied entry by entry, so a matrix signal is tested element for element and each entry remembers its own past independently.
Ports
- Input – the signal u being watched, of any size [m,n].
- Output – the flag y, of the same size as the input: 1.0 on a sample that satisfies the test and 0.0 on one that does not. The block never reshapes a signal.
Parameters
- Initial Condition (Previous Input) – the value standing in for u[−1] on the first sample, a scalar applied to every entry. Defaults to 0, as in Simulink.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The initial condition is baked in as the state seed rather than exposed as a tunable parameter, since it only affects the first sample of a run.
On the three HDL targets the comparison is made in the Q16.16 fixed-point datapath, so two consecutive samples closer together than one quantum (≈1.5×10−5) read as equal. That is a property of the datapath rather than of this block, and it is why the exported core is bit-exact against the reference for signals that move by more than a quantum between samples.
Simulink bridge
Import and export, mapped to simulink/Logic and Bit Operations/Detect Change.
"Initial Condition (Previous Input)" to vinit. The Simulink counterpart has
no SampleTime parameter – it is a masked subsystem that inherits
the rate of whatever drives it – so "Sampling Time (s)" does not cross, and a block
configured with an explicit positive rate reports that it did not carry over.
Simulink's InputProcessing is always implied as Elements as channels
(sample based): an ICore signal has no frame dimension, so treating columns as channels
has nothing to mean here, and pinning it is what stops an imported frame-based block from
being silently read as a sample-based one.
Notes
- Stateful and discrete only: one sample of memory per entry, holding the previous input.
- Not linear, and so deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing a comparison.
- Any change counts, up or down. For a one-directional test use Detect Increase or Detect Decrease.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Logic_And_Bit_Operations/Detect_Change |
| family | Control_Systems/Logic_And_Bit_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Detect_Change |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Detect_Change/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Detect_Change.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Detect_Change/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Detect_Change.h |
| default size on canvas | 90 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Initial Condition (Previous Input) | 0 | vinit |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Logic and Bit Operations/Detect Change |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | InputProcessing = Elements as channels (sample based) |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Initial Condition (Previous Input) | vinit | passes through |
Caveat (shown to the user): the sampling time does not cross: the Simulink counterpart is a masked subsystem with no SampleTime parameter, and inherits the rate of whatever drives it. InputProcessing is always implied as "Elements as channels (sample based)": an ICore signal has no frame dimension
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Detect Change -- the input differs from the previous sample in either direction y[k] = 1 when u[k] /= u[k-1], and 0 when the sample is unchanged, entry by entry. See the header for what the one sample of memory holds, and ICoreEdgeDetectBlock.h for the ten backends every block in this family shares.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.