Compare To Zero — Control Systems/Logic And Bit Operations
Control_Systems/Logic_And_Bit_Operations/Compare_To_Zero · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Compare To Zero
Control Systems / Logic And Bit Operations
Tests every entry of its input against zero with one relational operator and answers 1 where the test holds and 0 where it does not: y = (u <relop> 0). The comparison is applied entry by entry, so a matrix signal is treated element for element and the signal's size is unchanged.
Ports
- Input – the signal u to be tested, of any size [m,n].
- Output – y, of the SAME size [m,n] as the input. Every entry is 1 or 0. It is carried as an ordinary real signal, not a boolean type – every port in this library is a real matrix – so it can be fed straight into arithmetic as a 0/1 mask.
Parameters
- Operator – which comparison is made against zero. This selects
the test rather than retuning it, so each option is a separate code path.
- == (equal to zero) – 1 where the entry is exactly zero.
- ~= (not equal to zero) – the complement of the above.
- < (less than zero) – 1 for a strictly negative entry.
- <= (less than or equal to zero) – the same, and 1 at zero as well. This is the default, as in Simulink.
- >= (greater than or equal to zero) – 1 for a non-negative entry.
- > (greater than zero) – 1 for a strictly positive entry.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. The operator is a structural choice and is emitted
as the comparison itself rather than exposed as a tunable parameter, so a
generated core carries one test and not a switch over six. The three HDL targets
are fully synthesizable: a comparison against zero is a sign test on a Q16.16
word and needs no arithmetic, so nothing is evaluated in real.
Simulink bridge
Import and export, mapped to simulink/Logic and Bit Operations/Compare To
Zero. "Operator" to relop, one option for one option
(==, ~=, <, <=,
>=, >), so that round trip is lossless.
OutDataTypeStr is always written as boolean and
ZeroCross as off: this block has no data-type choice
to offer and no zero-crossing detection, and pinning both is what keeps the two
sides comparing the same thing.
The Simulink block defines no SampleTime parameter, so
"Sampling Time (s)" does not cross – a block left at the inheriting
default loses nothing, and one given an explicit period is reported rather than
silently dropped.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear – the output is a two-valued step function of the input – so the block deliberately carries no state space and model reduction reports it as unmergeable.
- == and ~= test for EXACT equality with zero. On a signal that arrived through any arithmetic that is a test almost nothing passes; they are useful on a signal that is quantized, counted or held, not on a continuous one.
- An HDL core sees its input already quantized to one part in 1.5×10⁻⁵, so an entry the software targets see just off zero can arrive at exactly zero and flip == and ~= at that sample. The four inequalities are affected only within one quantum of the boundary.
- To compare against a value other than zero, use Compare To Constant; to compare two signals, use Relational Operator.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Logic_And_Bit_Operations/Compare_To_Zero |
| family | Control_Systems/Logic_And_Bit_Operations |
| solver environment class | ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Compare_To_Zero |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Compare_To_Zero/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Compare_To_Zero.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Logic_And_Bit_Operations/Compare_To_Zero/ICoreBlock_0_Control_Systems_1_Logic_And_Bit_Operations_2_Compare_To_Zero.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Operator | == (equal to zero)%~%~= (not equal to zero)%~%< (less tha… | relop |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Logic and Bit Operations/Compare To Zero |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | OutDataTypeStr = boolean, ZeroCross = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Operator | relop | == (equal to zero) → ==, ~= (not equal to zero) → ~=, < (less than zero) → <, <= (less than or equal to zero) → <=, >= (greater than or equal to zero) → >=, > (greater than zero) → > |
Caveat (shown to the user): the six operators map 1:1 onto Simulink's relop values, so the choice is lossless in both directions; the Simulink block has NO SampleTime parameter, so "Sampling Time (s)" does not cross
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Compare To Zero block -- one relational test against zero, entry by entry y = 1 where (u <relop> 0) holds and y = 0 where it does not, with <relop> one of ==, ~=, <, <=, >= and > chosen by the "Operator" config. Applied INDEPENDENTLY to every entry of the input signal, so the output keeps the input's size.
The output is a REAL signal carrying 1.0 and 0.0, not a boolean type -- every port in this library is ICoreDouble. Simulink's counterpart emits a
boolean, which logs as 1/0, so the two agree numerically; the bridge pins OutDataTypeStr to boolean so that stays true.Code export: the operator is a STRUCTURAL choice, so each one is a separate emitted body rather than a tunable parameter. Nothing is baked in beyond the comparison itself -- the right-hand side is the literal zero.
HDL: fully synthesizable. A comparison against zero is a sign/zero test on a Q16.16 word and needs no arithmetic at all, so the three HDL cores stay in the fixed-point datapath. The one caveat is the datapath's, not the block's: a Q16.16 input is already quantized to 1.5e-5, so an entry that the software targets see just off zero can arrive at exactly zero and flip == and ~=. See the block's description, and the rig's config note.
Algebraic and stateless. No state space -- see the header.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.