Combinatorial Logic — Control Systems/Logic And Bit Operations

Combinatorial Logic

Control Systems / Logic And Bit Operations

Reads its input as a binary word and outputs the matching row of a truth table:

index = Σ over k of (u[k] is nonzero) · 2^(n-1-k), and y = row index of the table.

The first element of the input is the most significant bit and the index is 0-based, so a four-element input of [1 0 1 1] selects row 11. True means nonzero, not "equals one" – a negative element is true. Both are Simulink's conventions, measured rather than assumed.

Ports

• Input – the word u. It must carry exactly n elements, where the truth table has 2ⁿ rows; a mismatch stops the run rather than padding or truncating. Elements are read first-to-last (row-major), so either vector orientation reads the same.
• Output – y, the selected row as a column of m entries, where m is the table's COLUMN count. Its size comes from the table, not from the input, so this is one of the few blocks whose output size does not follow its input's.

Parameters

• Truth Table – the table itself, one row per input combination. Its row count must be a power of two (2, 4, 8, 16, …) and that is what fixes the input width. Rows run from the all-false combination downwards, so row 0 is the answer for all-zero input and the last row the answer for all-nonzero. Entries are ordinary numbers – nothing restricts them to 0 and 1. The default is [0; 1]: one input bit, one output, answering "is the input nonzero". Simulink's own default is a wider table, and the difference is deliberate – the value always crosses the bridge explicitly, and a narrow default is the one that works the moment the block is dropped on a canvas and fed a scalar.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The table is baked in at export time rather than exposed as a tunable parameter: its shape fixes the block's port widths, so it could not be retuned on a deployed core without re-generating it.

The targets divide in two. The seven software targets embed the table as an array and index it. The three HDL targets and PLC Structured Text emit one branch per row instead, because a fixed-point table has to become source literals and there is no array to index at run time. Both compute the same index from the same nonzero tests. The consequence worth knowing before choosing a wide table: on those four targets the generated code grows with the ROW COUNT, so an eight-bit table is 256 branches. The HDL cores are otherwise fully synthesizable – the only arithmetic is a comparison against zero.

Simulink bridge

Import and export, mapped to simulink/Logic and Bit Operations/Combinatorial Logic. "Truth Table" maps to TruthTable, and "Sampling Time (s)" to SampleTime, as on every block. The mapping is 1:1 and lossless.

One difference is worth stating because it does not cross and cannot: Simulink's block requires a boolean input port and refuses a double outright, so a Simulink model feeding it from arithmetic needs a Data Type Conversion in front. Here every signal is a matrix of doubles and the nonzero test does that job, which is why the two agree numerically without agreeing about types.

Notes

• Algebraic, with no state: the output depends only on the current sample.
• Deliberately carries no state space. A table lookup keyed on thresholded inputs is not a linear map, so model reduction reports the block as unmergeable rather than absorbing it.
• On the three HDL targets an input element within one Q16.16 quantum (about 1.5×10^-5) of zero can be carried across the boundary by the port's own quantization and flip that bit – and one flipped bit selects a different row. This is the window every block in this family carries: it is a property of testing a pre-quantized value against a threshold, not a fault in the generated code, and the seven software targets are exact everywhere.