Varying Delay — Control Systems/Linear Parameter Varying

Varying Delay

Control Systems / Linear Parameter Varying

Delays the input by an amount that is itself a signal, and interpolates between the two stored samples either side of it:

y(t) = u(t − T_d(t))

Whatever the delay port reads at time t is how far back the block reaches on that tick. The delay is given in seconds; a delay that falls between two samples is a linear blend of them, weighted by how far between them it lands, so the output moves smoothly as the delay sweeps rather than jumping a whole sample at a time. A delay of zero is direct feedthrough.

This is what distinguishes it from Variable Time Delay, which is otherwise the same idea: that block rounds the delay to the nearest whole sample, a documented approximation, and so steps its output as the delay crosses a half-sample boundary. Reach for this one inside a parameter-varying model, where the delay is a scheduling signal that moves continuously, and for that one when whole-sample resolution is enough.

Its sibling Variable Transport Delay reads the same port as a transit rate and integrates it instead – a different block, not a different setting.

Ports

• u – the delayed signal, of any size [m,n]. This is what comes out delayed.
• d – the delay in seconds, a scalar [1,1]. It applies to the whole signal, not per entry. Negative values are clamped to zero – nothing arrives before it was sent – and values beyond Maximum Delay (s) are clamped to it.
• Output – the delayed signal, the SAME size [m,n] as u.

Parameters

• Maximum Delay (s) – scalar, the longest delay the block can represent, in seconds. Defaults to 10, matching Simulink. It sets the depth of the transit line: a requested delay beyond it is clamped rather than growing the buffer, because a line that reallocates mid-run is a latency spike on a real target. Cost is proportional – at a 0.01 s rate the default is 1000 stored samples per signal entry – so set it to the largest delay you actually need rather than leaving headroom.
• Initial Output – scalar, what the block emits while the delay still reaches back past the start of the run. Defaults to 0. The whole buffer is pre-filled with it, so a run starts from a defined line rather than from samples that were never taken.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is the spacing of the samples the blend interpolates between, and the unit the maximum delay is counted in, so it is part of the arithmetic and not merely a schedule. A shorter step brings the two blended samples closer together and so tracks a fast-moving delay more faithfully.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each carries the ring buffer as its state, pre-filled with the initial output, and performs the same two-slot blend as the simulation. Only 1/dt and the depth are baked in as constants; the delay itself is read from its port every tick.

The three HDL targets carry the line as a slot × element register file and derive the read address in hardware, using the generated fixed-point package's fx_to_int – an arithmetic shift by the fraction width, which is floor() and so splits the delay the same way the software targets do; the fraction left over is one Q16.16 multiply. A zero whole part is special-cased to the input rather than read back from the buffer: the write is registered, so on that tick the addressed slot still holds its previous contents, and reading it would return the value from a whole lap ago instead of the sample just written. The OLDER of the two slots is never the one being written, so it always reads correctly. Note that the register file is sized from Maximum Delay (s), so a generous bound is paid for in flip-flops – keep it tight for a synthesizable core.

Note that on the HDL targets the delay arrives already quantized to the Q-format, one quantum being about 1.5×10⁻⁵, and the blend weight is carried in the same format. That shows up as a small proportional error rather than as a jump: unlike the rounding sibling, where a quantum either side of a half-sample boundary selects a different sample entirely, here it only nudges the weight. It is inherent to carrying a time in fixed point, not a defect of the generated core.

Simulink bridge

Import and export, mapped to cstblocks/Linear Parameter Varying/Varying Delay. "Maximum Delay (s)" to TdMax, "Initial Output" to u0. The block always implies PadeOrder = 0, since the delay is realized as a true transit line and never as a Padé approximation, and TdMin = 0, since a negative delay is clamped to zero here rather than floored at a configured minimum. A Simulink block carrying either at a different value is reported on import rather than silently accepted.

TdFixed, bufsize and FixedBuffer have no ICore counterpart: the transit line is sized from Maximum Delay (s) and the sampling time rather than from a buffer length in samples.

This block has no SampleTime parameter in Simulink – it is continuous there, and the measured dialog carries neither SampleTime nor Ts – so "Sampling Time (s)" stays on the ICore side and does not cross. Its discrete sibling does carry one, under the name Ts.

⚠ The parity suite checks this bridge only at whole-sample delays, and that is a property of the harness rather than of the block: both sides are driven from From Workspace with interpolation off, so Simulink holds its input between samples while this block blends two distinct stored values. They disagree by construction on a fractional delay. The interpolation itself is certified by code-export verification, which compares against ICore's own solver and drives the delay port freely.

Notes

• Stateful: Maximum Delay / dt + 1 past values of the signal port.
• Discrete by nature – the line advances one slot per sample, so the block always runs at its own rate rather than being pushed through a continuous solver's stages.
• Sub-sample delay IS interpolated, linearly, between the two stored samples either side of it – which is the whole difference from Variable Time Delay. The blend is exact for a signal that is itself linear between samples, and approximates anything else; shorten the sampling time where that matters.
• Not linear in the state-space sense, and so deliberately carries no state space: a pure delay is the transcendental factor e^(−sd), which no finite A/B/C/D expresses, and a time-varying one is not even time-invariant.