Discrete Varying PID — Control Systems/Linear Parameter Varying

Discrete Varying PID

Control Systems / Linear Parameter Varying

A discrete-time PID controller with a filtered derivative whose four gains arrive as signals rather than as parameters, so the controller may be re-scheduled on every sample. It takes the error u and produces the control signal y, with two accumulators – the integrator x_I and the derivative filter x_F:

dTerm = N[k]·( D[k]·u[k] − x_F[k] )
Parallel:  y[k] = P[k]·u[k] + x_I[k] + dTerm
Ideal:     y[k] = P[k]·( u[k] + x_I[k] + dTerm )
x_I[k+1] = x_I[k] + T_s·I[k]·u[k]
x_F[k+1] = x_F[k] + T_s·dTerm

The output reads the accumulators before the update, and the update consumes the same dTerm the output used. That ordering is part of the specification, not an implementation detail.

Ports

• u – the error signal, of any size [p,q]. The controller is SISO and is applied independently to every entry, each carrying its own x_I and x_F.
• P – the proportional gain for this sample, a scalar shared by every entry of u.
• I – the integral gain for this sample, a scalar. Zero removes the integral action for that sample.
• D – the derivative gain for this sample, a scalar. Zero removes the derivative action, whatever N is.
• N – the derivative filter bandwidth for this sample, a scalar. The filter pole is 1 − T_s·N, so N must stay in (0, 2/T_s) for the filter state to decay – see the Notes.
• Output – y, the same size as u.

The port order is Simulink's own: (u, P, I, D, N).

Parameters

• Controller Form – how P enters the sum:
  • Parallel – P, I and D are independent gains on the three branches.
  • Ideal – P multiplies the whole controller, so it scales the integral and derivative action too.
• Initial Condition (Integrator) – the integrator accumulator at the start of the run, a scalar used for every entry. The I gain sits before the integrator, so this is the initial value of the integral term, not of the accumulated error.
• Initial Condition (Filter) – the derivative filter's accumulator at the start of the run, a scalar used for every entry. Because the filter method is pinned to Forward Euler (see Notes), it is expressed in exactly the same units Simulink expresses it in, with no conversion on either side.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is not merely a schedule here: it is the T_s in both accumulators, so changing it changes the controller.

Everything else about the controller arrives on ports.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The gains are emitted as reads of the P/I/D/N signals rather than as constants, so a generated core re-schedules with them exactly as the simulation does; the only literals baked in are the sampling period, the chosen form and the two initial conditions. Nothing is discretized on the way out – the block is already a difference equation, so the core runs the identical recursion.

The three HDL targets carry the recursion in Q16.16 fixed point, which is possible only because the methods are pinned: any other choice would put a division by 1 + N[k]·c_F inside the sample loop and cost a fixed-point divider per entry per sample. Verilog and SystemVerilog round rather than truncate when bringing an accumulator increment back down – T_s·I·u is small against one Q16.16 quantum, and a truncation would bias every step the same way and walk the integrator off over a long run.

Simulink bridge

Import and export, mapped to cstblocks/Linear Parameter Varying/Discrete Varying PID (the library is cstblocks, not the "Control System Toolbox" display name, which add_block does not accept). "Controller Form" to Form (a 1:1 and therefore lossless pair), "Initial Condition (Integrator)" to InitialConditionForIntegrator and "Initial Condition (Filter)" to InitialConditionForFilter. The four gains need no parameter mapping at all – on both sides they are signals – and the port order is identical.

"Sampling Time (s)" crosses as SampleTime, under the standard name. That is worth stating because it is the exception in this family: every other Linear Parameter Varying block calls its rate Ts. This one does not, because underneath it is the stock PID Controller with ControllerParametersSource = external, which is what moves P/I/D/N onto ports.

Eleven further Simulink parameters are always implied, with no config behind them: ControllerParametersSource = external, TimeDomain = Discrete-time, Controller = PID, IntegratorMethod = Forward Euler, FilterMethod = Forward Euler, UseFilter = on, InitialConditionSource = internal, UseExternalDerivativeSource = off, UseKiTs = off, LimitOutput = off, AntiWindupMode = none, ExternalReset = none and TrackingMode = off. Every one of them either defines the block as the varying one rather than the stock one, or would add an input port in Simulink that no config value here can add.

Notes

• Discrete only, and stateful: two accumulators per entry of u.
• The two discretization methods are pinned to Forward Euler, which is Simulink's own default on this block. The alternatives (Backward Euler, Trapezoidal) divide by 1 + N[k]·c_F inside the sample loop, which a varying N cannot fold away at export time, and they make the filter initial condition ambiguous – Simulink scales it by N·T_s/(1 + N·c_F), and there is no single N to use. At Forward Euler that scale is exactly 1. Use Discrete PID Controller for the other eight integrator × filter combinations, with constant gains.
• Stability is the user's responsibility, in a way it is not on a fixed-gain controller. The filter pole is 1 − T_s·N, so an N outside (0, 2/T_s) – a negative one in particular – makes x_F grow, and nothing here can prevent it: N is a signal and its trajectory is not known until the run.
• Integrator wind-up is not limited. With no output saturation to unwind against, a sustained error accumulates without bound – the same behaviour Simulink's block has with LimitOutput off.
• Being time-varying, the block carries no state space and the model reduction and linear-analysis commands correctly refuse it. Use Discrete PID Controller when the gains are constant: it is linear, mergeable, and bakes the gains into the generated code.