Discrete Varying Lowpass — Control Systems/Linear Parameter Varying
Control_Systems/Linear_Parameter_Varying/Discrete_Varying_Lowpass · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Discrete Varying Lowpass
Control Systems / Linear Parameter Varying
A first-order lowpass filter w0/(s + w0) whose cutoff arrives on a port, so it may be re-tuned on every sample. It is discretized by the bilinear (Tustin) rule and realized in transposed direct form II. With a = Ts·w0[k]/2:
b0 = b1 = a/(1+a), a1 = −(1−a)/(1+a)
y[k] = b0·u[k] + s[k−1]
s[k] = b1·u[k] − a1·y[k]
Ports
- u – the signal to filter, of any size [p,q]. The filter is SISO and applied independently to every entry, each carrying its own state s, but all entries share the one cutoff.
- w0 – the cutoff in radians per second, scalar, for this sample. Zero freezes the output (a = 0 makes the filter pass nothing and hold its state); negative values are not meaningful and are not rejected, exactly as in Simulink.
- Output – y, the same size as u.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is also the Ts the Tustin coefficients are formed from, so it changes the filter and not merely how often it runs.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The cutoff is read from the port each step and the coefficients are formed there, so a generated core re-tunes exactly as the simulation does; only Ts is baked in.
The three HDL targets are SIMULATION-ONLY. Forming b0 and
a1 needs a division by (1+a) on every sample, which does not
belong in a Q16.16 datapath, so those cores carry the filter in real
arithmetic and quantize only at the port boundary. They simulate correctly and
are not offered as synthesizable – the same choice Recursive IIR and
Variable Transport Delay make.
Simulink bridge
Import and export, mapped to cstblocks/Linear Parameter Varying/Discrete
Varying Lowpass (the library is cstblocks, not the "Control
System Toolbox" display name, which add_block does not accept). The
cutoff needs no parameter mapping – on both sides it is a signal –
and the port order (u, w0) is identical.
Two parameters are always written out fixed. N = 1,
because it is the filter ORDER and moves ports, while an ICore port list is
structural. w0 = 0, because on the varying block the cutoff
comes from the port: leaving the parameter free would let an imported block
carry a second, silently unused cutoff.
"Sampling Time (s)" DOES cross, under Simulink's own name for it here:
this block's rate parameter is Ts, not SampleTime.
Emitting the standard name would be a hard set_param error that
aborts the whole generated script.
Notes
- Discrete only, and stateful: a single state s per entry, starting at zero.
- The discretization and the realization are both part of the specification. Tustin in transposed direct form II matches Simulink to 2·10−16 with w0 moving; the same Tustin filter written as a direct y-recursion is out by ~0.05, and Backward or Forward Euler by 0.25 to 0.33. The first pair differ ONLY once the cutoff moves, so a fixed-cutoff check cannot tell them apart.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Linear_Parameter_Varying/Discrete_Varying_Lowpass |
| family | Control_Systems/Linear_Parameter_Varying |
| solver environment class | ICoreBlock_0_Control_Systems_1_Linear_Parameter_Varying_2_Discrete_Varying_Lowpass |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Linear_Parameter_Varying/Discrete_Varying_Lowpass/ICoreBlock_0_Control_Systems_1_Linear_Parameter_Varying_2_Discrete_Varying_Lowpass.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Linear_Parameter_Varying/Discrete_Varying_Lowpass/ICoreBlock_0_Control_Systems_1_Linear_Parameter_Varying_2_Discrete_Varying_Lowpass.h |
| default size on canvas | 130 × 90 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | w0 |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | cstblocks/Linear Parameter Varying/Discrete Varying Lowpass |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| rate parameter name | Ts |
| always set | N = 1, w0 = 0 |
Caveat (shown to the user): the cutoff is a signal on both sides, so nothing about it is a parameter to carry, and the port order (u, w0) is identical; the filter ORDER is fixed at 1, because Simulink's N moves ports and an ICore port list is structural
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Discrete Varying Lowpass — w0/(s + w0) with the cutoff on a port, Tustin, transposed DF-II a = Ts*w0[k]/2 ; b0 = b1 = a/(1+a) ; a1 = -(1-a)/(1+a) y[k] = b0*u[k] + s[k-1] s[k] = b1*u[k] - a1*y[k]
Discretization AND realization were both measured against the R2026a block with w0 varying — see the header for the five candidates and their errors. Simulation and all ten exports carry the identical per-sample coefficient formation and the same single state s.
The three HDL targets run this in
realarithmetic and are SIMULATION-ONLY, quantizing only at the port boundary: forming b0/a1 needs a DIVISION by (1+a) on every sample, which does not belong in a Q16.16 datapath. Same call Recursive IIR and Variable Transport Delay make, and the description says so where a user will read it.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0.0907 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.66 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 4.026 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | 0.2222 … 6.951 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Linear_Parameter_Varying__Discrete_Varying_Lowpass.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).