Discrete Varying 2DOF PID — Control Systems/Linear Parameter Varying
Control_Systems/Linear_Parameter_Varying/Discrete_Varying_2DOF_PID · 8 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Discrete Varying 2DOF PID
Control Systems / Linear Parameter Varying
A two-degree-of-freedom discrete PID controller with a filtered derivative whose six parameters – the gains P, I, D, N and both setpoint weights b and c – arrive as signals, so the controller may be re-scheduled on every sample. It takes the reference r and the measurement y on separate ports rather than a pre-formed error, which is what lets the weights route the reference into the three branches independently:
eP = b[k]·r[k] − y[k], eI = r[k] − y[k], eD = c[k]·r[k] − y[k]
dTerm = N[k]·( D[k]·eD − xF[k] )
Parallel: u[k] = P[k]·eP + xI[k] + dTerm
Ideal: u[k] = P[k]·( eP + xI[k] + dTerm )
xI[k+1] = xI[k] + Ts·I[k]·eI
xF[k+1] = xF[k] + Ts·dTerm
b = c = 1 collapses the block to Discrete Varying PID. The point of the block is b < 1, which softens the proportional kick on a setpoint step without touching the disturbance response, and c = 0, which removes derivative kick entirely. The output reads the accumulators before the update, and the update consumes the same dTerm the output used.
Ports
- r – the reference / setpoint, of any size [p,q].
- y – the measurement, the same size as r. The controller is SISO and is applied independently to every entry, each carrying its own xI and xF.
- P – the proportional gain for this sample, a scalar shared by every entry.
- I – the integral gain for this sample, a scalar.
- D – the derivative gain for this sample, a scalar. Zero removes the derivative action, whatever N is.
- N – the derivative filter bandwidth for this sample, a scalar. The filter pole is 1 − Ts·N – see the Notes.
- b – the proportional setpoint weight for this sample, a scalar.
- c – the derivative setpoint weight for this sample, a scalar.
- Output – u, the same size as r.
The port order is Simulink's own: (r, y, P, I, D, N, b, c).
Parameters
- Controller Form – how P enters the sum:
- Parallel – P, I and D are independent gains on the three branches, so the reference feedthrough is P·b + N·D·c.
- Ideal – P multiplies the whole controller, so it scales the integral and derivative action and the setpoint-weighted proportional term: the reference feedthrough becomes P·(b + N·D·c).
- Initial Condition (Integrator) – the integrator accumulator at the start of the run, a scalar used for every entry. The I gain sits before the integrator, so this is the initial value of the integral term.
- Initial Condition (Filter) – the derivative filter's accumulator at the start of the run, a scalar used for every entry. Because the filter method is pinned to Forward Euler (see Notes), it is expressed in exactly the same units Simulink expresses it in, with no conversion on either side.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is the Ts in both accumulators, so changing it changes the controller.
Everything else about the controller arrives on ports.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The six parameters are emitted as reads of their signals rather than as constants, so a generated core re-schedules with them exactly as the simulation does; the only literals baked in are the sampling period, the chosen form and the two initial conditions. Nothing is discretized on the way out – the block is already a difference equation.
The three HDL targets carry the recursion in Q16.16 fixed point, which is possible only because the methods are pinned: any other choice would put a division by 1 + N[k]·cF inside the sample loop. Verilog and SystemVerilog round rather than truncate when bringing an accumulator increment back down, since Ts·I·eI is small against one Q16.16 quantum and a truncation would bias every step the same way.
Simulink bridge
Import and export, mapped to cstblocks/Linear Parameter Varying/Discrete
Varying 2DOF PID (the library is cstblocks, not the "Control
System Toolbox" display name, which add_block does not accept).
"Controller Form" to Form (a 1:1 and therefore lossless pair),
"Initial Condition (Integrator)" to InitialConditionForIntegrator and
"Initial Condition (Filter)" to InitialConditionForFilter. The six
parameters need no mapping at all – on both sides they are signals, so
Simulink's own b and c parameters are inert here –
and the port order is identical.
"Sampling Time (s)" crosses as SampleTime, under the
standard name. That is worth stating because it is the exception in this family:
every other Linear Parameter Varying block calls its rate Ts. This one
does not, because underneath it is the stock PID Controller (2DOF) with
ControllerParametersSource = external, which is what moves the
six parameters onto ports.
Thirteen further Simulink parameters are always implied, with no config behind
them: ControllerParametersSource = external,
TimeDomain = Discrete-time, Controller =
PID, IntegratorMethod = Forward Euler,
FilterMethod = Forward Euler, UseFilter =
on, InitialConditionSource = internal,
UseExternalDerivativeSource = off, UseKiTs =
off, LimitOutput = off, AntiWindupMode =
none, ExternalReset = none and
TrackingMode = off. Every one of them either defines the block
as the varying one rather than the stock one, or would add an input port in
Simulink that no config value here can add.
Notes
- Discrete only, and stateful: two accumulators per entry of r.
- The two discretization methods are pinned to Forward Euler, which is Simulink's own default on this block. The alternatives (Backward Euler, Trapezoidal) divide by 1 + N[k]·cF inside the sample loop, which a varying N cannot fold away at export time, and they make the filter initial condition ambiguous – Simulink scales it by N·Ts/(1 + N·cF), and there is no single N to use. At Forward Euler that scale is exactly 1. Use Discrete PID Controller for the other eight integrator × filter combinations, with constant gains.
- Stability is the user's responsibility. The filter pole is 1 − Ts·N, so an N outside (0, 2/Ts) makes xF grow, and nothing here can prevent it: N is a signal and its trajectory is not known until the run.
- Integrator wind-up is not limited – the same behaviour Simulink's block
has with
LimitOutputoff. - Being time-varying, the block carries no state space and the model reduction and linear-analysis commands correctly refuse it. Use PID Controller (2DOF) or Discrete PID Controller when the parameters are constant.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Linear_Parameter_Varying/Discrete_Varying_2DOF_PID |
| family | Control_Systems/Linear_Parameter_Varying |
| solver environment class | ICoreBlock_0_Control_Systems_1_Linear_Parameter_Varying_2_Discrete_Varying_2DOF_PID |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Linear_Parameter_Varying/Discrete_Varying_2DOF_PID/ICoreBlock_0_Control_Systems_1_Linear_Parameter_Varying_2_Discrete_Varying_2DOF_PID.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Linear_Parameter_Varying/Discrete_Varying_2DOF_PID/ICoreBlock_0_Control_Systems_1_Linear_Parameter_Varying_2_Discrete_Varying_2DOF_PID.h |
| default size on canvas | 150 × 160 px |
| ports at insert | 8 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | r |
| 2 | in | ICoreDouble | y |
| 3 | in | ICoreDouble | P |
| 4 | in | ICoreDouble | I |
| 5 | in | ICoreDouble | D |
| 6 | in | ICoreDouble | N |
| 7 | in | ICoreDouble | b |
| 8 | in | ICoreDouble | c |
| 9 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Controller Form | Parallel%~%Ideal~~Parallel | Form |
Initial Condition (Integrator) | 0 | InitialConditionForIntegrator |
Initial Condition (Filter) | 0 | InitialConditionForFilter |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | cstblocks/Linear Parameter Varying/Discrete Varying 2DOF PID |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | ControllerParametersSource = external, TimeDomain = Discrete-time, Controller = PID, IntegratorMethod = Forward Euler, FilterMethod = Forward Euler, UseFilter = on, InitialConditionSource = internal, UseExternalDerivativeSource = off, UseKiTs = off, LimitOutput = off, AntiWindupMode = none, ExternalReset = none, TrackingMode = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Controller Form | Form | Parallel → Parallel, Ideal → Ideal |
Initial Condition (Integrator) | InitialConditionForIntegrator | passes through |
Initial Condition (Filter) | InitialConditionForFilter | passes through |
Caveat (shown to the user): the four gains AND both setpoint weights are signals on both sides, so none of them is a parameter to carry (Simulink's own b and c parameters are inert on this block) and the port order (r, y, P, I, D, N, b, c) is identical; the integrator and filter methods are PINNED to Forward Euler (Simulink's own default here) because any other choice puts a division by 1 + N*cF inside the sample loop, which a varying N cannot fold away at export time, and makes InitialConditionForFilter ambiguous -- use Discrete PID Controller for the other eight combinations; output saturation/anti-windup, external reset, an external derivative source, external initial conditions and tracking mode are not supported, each adding an input port in Simulink that no config value here can add
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Discrete Varying 2DOF PID — a two-degree-of-freedom discrete PID whose six parameters are SIGNALS eP = b*r - y eI = r - y eD = c*r - y dTerm = N*(D*eD - xF) u[k] = P*eP + xI + dTerm (Parallel) u[k] = P*( eP + xI + dTerm ) (Ideal) xI[k+1] = xI + Ts*I*eI xF[k+1] = xF + Ts*dTerm
The realization is Simulink's, reused from Control_Systems/Discrete/Discrete_PID_Controller at Forward Euler rather than re-derived -- see the header, including why both methods are pinned and what the Ideal form does to the setpoint weighting.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0 |
ramp | Ramp: slope 1 from t = 0 | -0.2358 … 249.3 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1.473 … 1.943 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -40.76 … 63.46 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Linear_Parameter_Varying__Discrete_Varying_2DOF_PID.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).