Decrement Stored Integer — Control Systems/Increment Decrement
Control_Systems/Increment_Decrement/Decrement_Stored_Integer · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Decrement Stored Integer
Control Systems / Increment Decrement
Subtracts one from the signal's stored integer: y = u − 1, applied entry by entry. On a floating-point signal the stored integer IS the value – there is no scaling between the two – so this block computes exactly what Decrement Real World computes. It exists so that a model imported from Simulink keeps the block its author chose, and so that the distinction survives a round trip.
Ports
- Input – the signal u, of any size [m,n].
- Output – y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- None. The step of one is the block itself, not a setting: to subtract any other constant use Bias with a negative offset, and to subtract a signal use Subtract.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. The step is inlined as the literal 1
rather than exposed as a tunable parameter – there is no parameter behind
it to tune. The three HDL targets carry the arithmetic in Q16.16 fixed point and
are fully synthesizable: adding two values of the same format needs no shift and
no function call.
Simulink bridge
Import and export, mapped to simulink/Additional Math & Discrete/Additional Math: Increment - Decrement/Decrement Stored Integer. There are no parameters to map in either direction: Simulink's counterpart is a masked subsystem whose dialog and mask parameter lists are both empty.
The rate does NOT cross. That same block defines no
SampleTime parameter, so "Sampling Time (s)" stays on the ICore
side; writing it anyway would be a hard set_param error that aborts
the generated script rather than a warning.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Affine, not linear, so the block deliberately carries no state space. y = u − 1 does not pass through the origin and A/B/C/D has nowhere to hold the constant – model reduction reports it as unmergeable rather than absorbing an offset it cannot represent. This is Bias's reasoning, not Abs's.
- Identical to Decrement Real World on every ICore signal. The two differ only for fixed-point data types, where one step of the stored integer is one quantum of the scaling rather than one whole unit. Every ICore signal is a double, so the distinction has no numerical effect here – it is carried for the Simulink bridge's sake, not the solver's.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Increment_Decrement/Decrement_Stored_Integer |
| family | Control_Systems/Increment_Decrement |
| solver environment class | ICoreBlock_0_Control_Systems_1_Increment_Decrement_2_Decrement_Stored_Integer |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Increment_Decrement/Decrement_Stored_Integer/ICoreBlock_0_Control_Systems_1_Increment_Decrement_2_Decrement_Stored_Integer.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Increment_Decrement/Decrement_Stored_Integer/ICoreBlock_0_Control_Systems_1_Increment_Decrement_2_Decrement_Stored_Integer.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Additional Math & Discrete/Additional Math: Increment - Decrement/Decrement Stored Integer |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the rate does not cross: the Simulink block is a masked subsystem with no SampleTime parameter, so "Sampling Time (s)" stays on the ICore side
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Decrement Stored Integer block -- subtract one from the signal y = u - 1, entry by entry, so the output keeps the input's size. Algebraic, stateless, and with no parameters at all: the step of one is what the block IS. Deliberately carries no state space -- the relation is AFFINE, not linear (see the header).
Code export: the step is inlined as the literal 1 in all ten targets. There is nothing to expose as a tunable parameter, because a block whose step could be retuned would be a Bias.
Simulink's counterpart is a MASKED SUBSYSTEM ("Stored Integer Value Decrement") with NO dialog parameters and NO mask parameters at all -- verified with get_param(blk,'DialogParameters') and get_param(blk,'MaskNames') against R2026a, both empty. So the bridge entry carries an empty params list, and hasSampleTimeParam is false: set_param(blk,'SampleTime',...) on it is the hard MATLAB error "... block (mask) does not have a parameter named 'SampleTime'", which aborts a whole generated script rather than degrading.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -3 |
| 0.4 | 0.5 | -0.5 |
| 0.8 | -2 | -3 |
| 1.2 | 0.5 | -0.5 |
| 1.6 | -2 | -3 |
| 2 | 0.5 | -0.5 |
| 2.4 | -2 | -3 |
| 2.8 | 0.5 | -0.5 |
| 3.2 | -2 | -3 |
| 3.6 | 0.5 | -0.5 |
| 4 | -2 | -3 |
| 4.4 | 0.5 | -0.5 |
| 4.8 | -2 | -3 |
| 5.2 | 0.5 | -0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -1 … 0 |
ramp | Ramp: slope 1 from t = 0 | -1 … 4.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -2 … -4.264e-4 |
step | Step: 0 -> 1 at t = 1 s | -1 … 0 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Increment_Decrement__Decrement_Stored_Integer.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).