Zero Order Hold — Control Systems/Discrete

Zero-Order Hold

Control Systems / Discrete

Samples its input at the block's own rate and holds that value until the next sample:

y(t) = u[k]  for  k·T_s ≤ t < (k+1)·T_s

As a transfer function it is simply H(z) = 1. The whole block is its sampling time: it has no coefficient to configure and keeps no memory of past samples, so what it contributes is a rate, not arithmetic. Put one in front of a subsystem that must run slower than the model around it, or use it to model the sampler a digital controller sees the continuous world through.

Ports

• Input – the signal u to sample, of any size [p,m].
• Output – the held signal y, the SAME size [p,m] as the input. Every entry is sampled on the same tick; the block does not stagger them.

Parameters

• Sampling Time (s) – the only parameter, and the block's entire behaviour. A positive value is the period the input is sampled at, and the output holds between those instants. Zero or less inherits the solver's rate, at which point the block samples every step and is a straight wire – a zero-order hold only does something when it is slower than what surrounds it, so leaving this at the default makes the block a no-op rather than a bug.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, all from the shared realization every linear Control Systems / Discrete block uses. There is nothing to tune and nothing to bake in: the emitted body is a copy of the input to the output, and the holding is carried by the rate the generated core schedules the block at, exactly as it is in the in-app run.

Simulink bridge

Import and export, mapped to simulink/Discrete/Zero-Order Hold. There is one parameter on each side and they are the same one: "Sampling Time (s)" to SampleTime, through the global mapping every block uses. Nothing is left behind in either direction, which makes this the most complete crossing in the library – there is simply nothing else to carry.

Notes

• Discrete only, and stateless: the output is this sample's input, with no past value remembered. That is what separates it from Unit Delay, which holds the PREVIOUS sample and therefore adds a delay; a zero-order hold adds none.
• Being linear (indeed a pure feed-through), the block is directly usable by the model reduction and linear-analysis commands, which will absorb it into a neighbour rather than being blocked by it.
• It does nothing at the surrounding rate. Worth repeating, because a diagram that samples everything at one period gets an exact wire here and that is the correct result. Give the block a slower "Sampling Time (s)" than the model's for it to have any effect at all.