Unit Delay — Control Systems/Discrete
Control_Systems/Discrete/Unit_Delay · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Unit Delay
Control Systems / Discrete
Holds its input for one sample period, the z−1 operator:
y[k] = u[k−1]
Before the first sample has been taken there is no previous input, so the block emits the configured Initial Condition instead. This is the canonical unit of memory in a discrete diagram – a feedback path through one of these is what turns an algebraic loop into a recursion.
Ports
- Input – the signal u to delay, of any size [m,n]. The delay is applied entry by entry: every element is held for one sample, and the entries do not interact.
- Output – the delayed signal y, the SAME size [m,n] as the input.
Parameters
- Initial Condition – a scalar, what the block emits on the first sample, before any input has been stored. Defaults to 0. It is broadcast to every entry of the signal, so one value seeds a matrix signal whatever its size.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is the length of the delay, so it is part of the arithmetic and not merely a schedule.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each carries one held matrix as its state, seeded with the initial condition. The initial condition is baked into the generated core at export time rather than exposed as a tunable parameter, because it seeds a state rather than scaling arithmetic.
The three HDL targets need no special handling here, unlike the other delay blocks: the state write is a registered assignment, so reading the state signal within the same tick returns its pre-clock contents – which is exactly the previous sample this block is chartered to emit. The delay falls out of the register rather than having to be arranged around it.
Simulink bridge
Import and export, mapped to simulink/Discrete/Unit Delay. "Initial
Condition" to InitialCondition, and "Sampling Time (s)" to
SampleTime as on every block. The mapping is complete – there
is no ICore config left behind and no Simulink parameter left unset, which is
what makes this one of the cleanest crossings in the library.
Notes
- Stateful: one held matrix, the previous sample of the input.
- Discrete by nature – the state advances once per sample, so the block always runs at its own rate rather than being pushed through a continuous solver's stages.
- Unit Delay vs. Memory. Both compute y[k] = u[k−1] and the two are easy to confuse. The difference is the RATE: this block runs at its own "Sampling Time (s)" and delays by exactly that period, whereas Memory delays by one solver step and inherits its rate from the block driving it. Reach for Unit Delay whenever the delay length is something you want to state; reach for Memory when you want a break in an algebraic loop at whatever rate the surrounding model happens to run.
- Deliberately carries no state space. A pure delay is the
transcendental factor e^(−sTs), which no finite continuous
A/B/C/D expresses, so fabricating one would let the model-reduction commands
merge a delay into a plant as though it were a gain. Its discrete
realization is A=[0], B=[1], C=[1], D=[0], and the block runs that recursion
directly – carrying it as an
ICoreStateSpacewould fix the signal to a column vector and forbid the matrix signals this block accepts.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Unit_Delay |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Unit_Delay |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Unit_Delay/ICoreBlock_0_Control_Systems_1_Discrete_2_Unit_Delay.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Unit_Delay/ICoreBlock_0_Control_Systems_1_Discrete_2_Unit_Delay.h |
| default size on canvas | 90 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Initial Condition | 0 | InitialCondition |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Unit Delay |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Initial Condition | InitialCondition | passes through |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Unit Delay block — y[k] = u[k-1], the z^-1 operator One sample of memory. The block emits the PREVIOUS sample of its input and stores the current one for the next tick; before the first tick has been taken it emits the configured Initial Condition. The signal may be any size [m,n] and the output matches it exactly — the delay is applied entry by entry, with one held matrix rather than one held scalar.
y[k] = held (held = the initial condition until the first tick) held = u[k]
Discrete by nature: the line advances one slot per SAMPLE, so the block always takes its rate from its own "Sampling Time (s)" rather than being pushed through a continuous solver's stages. That is the difference between this block and Memory, which is otherwise the same recursion — see the description's Notes.
Code export: all ten targets. The recursion is the same everywhere, and on the three HDL backends it needs no special handling at all: the state write is REGISTERED, so reading the state signal in the same tick returns its pre-clock contents, which IS the previous sample. (Contrast Entity Transport Delay and First Order Hold, where the tick needs a value it is about to overwrite and has to take it from the pre-clock source instead.)
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.7 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 3 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Unit_Delay.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).