Transfer Fcn Real Zero — Control Systems/Discrete

Transfer Fcn Real Zero

Control Systems / Discrete

A single real zero given directly in the z plane, and effectively no pole:

H(z) = (z − Z) / z

realized as the one-line recursion y[k] = u[k] − Z·u[k−1]. The z in the denominator is only the one-sample delay that makes the zero causal – it contributes a unit of memory rather than a mode to the dynamics, and the recursion never feeds its own output back, which is why the block is described as having no pole. On the very first sample there is no previous input, so the configured initial condition stands in for it.

Ports

• Input – the signal u to filter, of any size [p,m].
• Output – the filtered signal y, the SAME size [p,m] as the input.

The zero is scalar, but it is applied independently to every entry of the input signal, each entry remembering its own previous value.

Parameters

• Zero (in Z Plane) – a scalar Z, the numerator's root. Defaults to 0.75, Simulink's own default. Z = 1 puts the zero on the unit circle at DC and makes the block a plain first difference; Z = 0 leaves a straight wire; a negative Z places the zero at half the sampling frequency. |Z| > 1 is a non-minimum-phase zero, which is accepted rather than rejected.
• Initial Condition (Previous Input) – a scalar standing in for u[−1] on the first sample, broadcast to every entry of the signal. Defaults to 0. Having no pole, the block forgets it completely after one sample: it affects the first output only.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, all from the shared realization every linear Control Systems / Discrete block uses. The zero and the initial condition are baked into the generated core at export time rather than exposed as tunable parameters: the zero is folded into the C coefficient, and the initial condition seeds a state rather than scaling arithmetic.

Simulink bridge

Import and export, mapped to simulink/Discrete/Transfer Fcn Real Zero. "Zero (in Z Plane)" to ZeroZ, "Initial Condition (Previous Input)" to ICPrevInput. Both cross as plain numbers, so the mapping is lossless in either direction.

InputProcessing is always emitted as Elements as channels (sample based), with no ICore config behind it, because that is what this block does and the alternative would mean something else entirely: ICore treats every entry of a [p,m] signal as its own independent channel, whereas Simulink's frame-based setting would read the columns as one channel's samples over time. A model importing with the other value is reported rather than quietly accepted.

"Sampling Time (s)" does not cross, unusually: Simulink's block is a masked subsystem with no SampleTime parameter at all, so the rate stays on the ICore side and a block configured with an explicit positive rate reports that it did not carry over. In Simulink it simply inherits the rate of whatever drives it.

Simulink's RndMeth and DoSatur are left at their defaults and have no ICore counterpart: they select a rounding mode and an overflow policy that only bite on fixed-point or integer signals, and ICore's signal path is double precision throughout.

Notes

• Discrete only, and stateful: one past sample per entry. Being an FIR section, it has no feedback at all, so any transient dies within one sample.
• Being linear, the block is directly usable by the model reduction and linear-analysis commands.
• Real Zero vs. Difference. Difference is exactly this block at Z = 1: y[k] = u[k] − u[k−1]. Reach for Difference when you want the sample-to-sample change; reach for this one when the zero belongs somewhere else in the plane.