Transfer Fcn First Order — Control Systems/Discrete

Transfer Fcn First Order

Control Systems / Discrete

A first-order lag whose pole is given directly in the z plane:

H(z) = (1 − P)·z / (z − P)

realized as the one-line recursion y[k] = P·y[k−1] + (1 − P)·u[k]. The numerator's (1 − P) is what makes H(1) = 1: whatever the pole, a constant input settles to itself, so P sets only how fast the block gets there and never how far. On the very first sample there is no previous output, so the configured initial condition stands in for it.

Ports

• Input – the signal u to filter, of any size [p,m].
• Output – the filtered signal y, the SAME size [p,m] as the input.

The transfer function is scalar, but it is applied independently to every entry of the input signal, each entry remembering its own previous output.

Parameters

• Pole (in Z Plane) – a scalar P, the single pole. Defaults to 0.95, Simulink's own default. |P| < 1 is a stable lag, and the closer to 1 the slower it settles; P = 0 makes the block a straight wire, and |P| > 1 diverges. It is not checked against the unit circle: an unstable pole is a legitimate thing to model.
• Initial Condition (Previous Output) – a scalar standing in for y[−1] on the first sample, broadcast to every entry of the signal. Defaults to 0. It decays away at the rate P rather than affecting one sample only, so on a slow pole it is visible for a long time.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, all from the shared realization every linear Control Systems / Discrete block uses. The pole and the initial condition are baked into the generated core at export time rather than exposed as tunable parameters: the pole is folded into the A/B/C/D coefficients, and the initial condition seeds a state rather than scaling arithmetic.

Simulink bridge

Import and export, mapped to simulink/Discrete/Transfer Fcn First Order. "Pole (in Z Plane)" to PoleZ, "Initial Condition (Previous Output)" to ICPrevOutput. Both cross as plain numbers, so the mapping is lossless in either direction.

"Sampling Time (s)" does not cross, unusually: Simulink's block is a masked subsystem with no SampleTime parameter at all, so the rate stays on the ICore side and a block configured with an explicit positive rate reports that it did not carry over. In Simulink it simply inherits the rate of whatever drives it.

Simulink's RndMeth and DoSatur are left at their defaults and have no ICore counterpart: they select a rounding mode and an overflow policy that only bite on fixed-point or integer signals, and ICore's signal path is double precision throughout.

Notes

• Discrete only, and stateful: one past output per entry.
• Being linear, the block is directly usable by the model reduction and linear-analysis commands.
• First Order vs. Lead or Lag. This block is the special case of Transfer Fcn Lead or Lag with the zero at the origin and the gain normalized, so reach for that one whenever the numerator needs a zero of its own.