Transfer Fcn Direct Form II — Control Systems/Discrete
Control_Systems/Discrete/Transfer_Fcn_Direct_Form_II · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Transfer Fcn Direct Form II
Control Systems / Discrete
A discrete IIR filter realized in direct form II – one shared delay line instead of separate input and output histories:
w[k] = u[k] − a1·w[k−1] − … − an·w[k−n]
y[k] = b0·w[k] + b1·w[k−1] + … + bm·w[k−m]
Equivalent to H(z) = B(z) / A(z) with A monic, but realized with the minimum number of delays – max(n,m) rather than n+m.
Ports
- Input – the signal u to filter, of any size [p,m].
- Output – y, of the SAME size [p,m]. The filter is SISO but is applied independently to every entry, each carrying its own delay line.
Parameters
- Numerator Coefficients – the row vector [b0 b1 … bm], in descending powers of z. All of it crosses.
- Denominator Coefficients – the row vector [a1 a2 … an]. The leading coefficient a0 is NOT listed: it is fixed at 1, so the denominator is monic by contract. This is the one convention to get right – the Discrete Transfer Function block next door takes a FULL denominator including its leading term, so a vector typed for one block is silently wrong in the other. Leave it empty for a pure FIR filter.
- Initial Condition – scalar, the value every entry's delay line holds before the first sample. Defaults to 0.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The coefficients are baked into the generated body at export time rather than exposed as tunable parameters, because changing the order would change the size of the delay line the core declares. The three HDL targets carry the recursion in Q16.16 fixed point like every other discrete block here.
Simulink bridge
Import and export, mapped to simulink/Additional Math & Discrete/
Additional Discrete/Transfer Fcn Direct Form II. "Numerator Coefficients"
to NumCoefVec, "Denominator Coefficients" to
DenCoefVec and "Initial Condition" to vinit, all as
plain pass-through values, so the round trip is lossless. Simulink's
RndMeth and DoSatur are always written as
Floor and off: both act on the block's fixed-point STORED type,
and this block is double precision throughout, so there is no ICore choice
behind them to carry. "Sampling Time (s)" does NOT cross – this
Simulink block defines no SampleTime parameter at all, so the rate
stays on the ICore side and a block given an explicit period reports that it
did not cross.
Notes
- Discrete only, and stateful: max(n,m) past values of w per entry.
- Direct form II uses fewer delays than direct form I but is more sensitive to coefficient quantization, which is why the fixed-point HDL exports of a high-order filter can drift from the double-precision reference where the software targets do not.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Transfer_Fcn_Direct_Form_II |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Transfer_Fcn_Direct_Form_II |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Transfer_Fcn_Direct_Form_II/ICoreBlock_0_Control_Systems_1_Discrete_2_Transfer_Fcn_Direct_Form_II.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Transfer_Fcn_Direct_Form_II/ICoreBlock_0_Control_Systems_1_Discrete_2_Transfer_Fcn_Direct_Form_II.h |
| default size on canvas | 130 × 90 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Numerator Coefficients | [0.2 0.3 0.2] | NumCoefVec |
Denominator Coefficients | [-0.9 0.6] | DenCoefVec |
Initial Condition | 0 | vinit |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Additional Math & Discrete/Additional Discrete/Transfer Fcn Direct Form II |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | RndMeth = Floor, DoSatur = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Numerator Coefficients | NumCoefVec | passes through |
Denominator Coefficients | DenCoefVec | passes through |
Initial Condition | vinit | passes through |
Caveat (shown to the user): the block runs at the surrounding Simulink rate; "Sampling Time (s)" does not cross, because this Simulink block defines no SampleTime parameter
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Transfer Fcn Direct Form II block — discrete IIR on ONE shared delay line w[k] = u[k] - a1*w[k-1] - ... - an*w[k-n] y[k] = b0*w[k] + b1*w[k-1] + ... + bm*w[k-m]
The denominator is monic by contract: "Denominator Coefficients" carries a1..an and the leading 1 is implied, matching Simulink's DenCoefVec. See the header for why that makes this a separate block rather than a mode of Discrete_Transfer_Function.
Simulation and every one of the ten exports realize the SAME recursion over the same delay line, applied independently to each [p,m] entry of the input signal.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -0.2402 … 0.512 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.743 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1.028 … 1.028 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2.199 … 2.741 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Transfer_Fcn_Direct_Form_II.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).