Transfer Fcn Direct Form II Time Varying — Control Systems/Discrete
Control_Systems/Discrete/Transfer_Fcn_Direct_Form_II_Time_Varying · 3 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Transfer Fcn Direct Form II Time Varying
Control Systems / Discrete
The direct form II IIR filter of the Transfer Fcn Direct Form II block, with the coefficients arriving on ports instead of config, so they may change on every sample:
w[k] = u[k] − a1[k]·w[k−1] − … − an[k]·w[k−n]
y[k] = b0[k]·w[k] + b1[k]·w[k−1] + … + bm[k]·w[k−m]
One shared delay line, max(n,m) deep, rather than the separate input and output histories a direct form I realization keeps.
Ports
- u – the signal to filter, of any size [p,q]. The filter is SISO and is applied independently to every entry, each carrying its own delay line, but all of them share the one coefficient pair below.
- Num – the numerator [b0 b1 … bm] for this sample, in descending powers of z. Its width is fixed by the link; only its values vary.
- Den – the denominator [a1 a2 … an] for this sample. The leading coefficient a0 is NOT carried: it is fixed at 1, so the denominator is monic by contract – Simulink names this very port Den No Lead. Feed it a 1×1 zero for a pure FIR filter.
- Output – y, of the same size as u.
Parameters
- Initial Condition – scalar, the value every entry's delay line holds before the first sample. Defaults to 0.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The coefficients are emitted as indexed reads of the Num and Den signals, not as constants, so a generated core varies with them exactly as the simulation does. What IS baked in is the number of taps and the depth of the delay line, both taken from the port widths at export time – ICore resolves a signal's size once, so a core cannot grow a tap at run time. The three HDL targets carry the recursion in Q16.16 fixed point; note that coefficients arriving on a port are quantized to that grid, where the fixed-coefficient block's are exact.
Simulink bridge
Import and export, mapped to simulink/Additional Math & Discrete/
Additional Discrete/Transfer Fcn Direct Form II Time Varying. "Initial
Condition" to vinit as a plain pass-through value; the
coefficients need no mapping at all, because on both sides they are signals
rather than parameters. The port order (u, Num, Den) is the same on both
sides. Simulink's RndMeth and DoSatur are always
written as Floor and off: both act on the block's fixed-point
STORED type, and this block is double precision throughout, so there is no ICore
choice behind them to carry. "Sampling Time (s)" does NOT cross –
this Simulink block defines no SampleTime parameter at all, so the
rate stays on the ICore side and a block given an explicit period reports that
it did not cross.
Notes
- Discrete only, and stateful: max(n,m) past values of w per entry of u.
- Stability is the user's responsibility here in a way it is not on the fixed-coefficient block. A denominator that wanders outside the stable region for even a few samples can start a divergence the filter never recovers from, and nothing in the block can prevent it: the coefficients are signals, and their trajectory is not known until the run.
- Use Transfer Fcn Direct Form II instead whenever the coefficients are constant. It bakes them into the generated code, which is both faster and exact, where this block must quantize them through the ports on the HDL targets.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Transfer_Fcn_Direct_Form_II_Time_Varying |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Transfer_Fcn_Direct_Form_II_Time_Varying |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Transfer_Fcn_Direct_Form_II_Time_Varying/ICoreBlock_0_Control_Systems_1_Discrete_2_Transfer_Fcn_Direct_Form_II_Time_Varying.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Transfer_Fcn_Direct_Form_II_Time_Varying/ICoreBlock_0_Control_Systems_1_Discrete_2_Transfer_Fcn_Direct_Form_II_Time_Varying.h |
| default size on canvas | 140 × 100 px |
| ports at insert | 3 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | Num |
| 3 | in | ICoreDouble | Den |
| 4 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Initial Condition | 0 | vinit |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Additional Math & Discrete/Additional Discrete/Transfer Fcn Direct Form II Time Varying |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | RndMeth = Floor, DoSatur = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Initial Condition | vinit | passes through |
Caveat (shown to the user): port order is (u, Num, Den) on both sides, and Den carries a1..an with the leading 1 implied (Simulink names the port "Den No Lead"); the block runs at the surrounding Simulink rate, so "Sampling Time (s)" does not cross, this Simulink block defining no SampleTime parameter
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Transfer Fcn Direct Form II Time Varying — the DF-II recursion with coefficients on PORTS w[k] = u[k] - a1[k]*w[k-1] - ... - an[k]*w[k-n] y[k] = b0[k]*w[k] + b1[k]*w[k-1] + ... + bm[k]*w[k-m]
Port order is (u, Num, Den) and the denominator is the TAIL a1..an with the leading 1 implied. Both facts were measured against the R2026a block, not assumed: its masked subsystem names the three inports
u,NumandDen No Lead, and driving u = 3, Num = [0.5 0], Den = [0] returns y = 1.5, which only the (u, Num, Den) assignment explains.Everything else follows Transfer_Fcn_Direct_Form_II next door, and deliberately so: the two blocks must realize the identical recursion, differing only in where the coefficients come from. What changes in the exports is that the taps are INDEXED SIGNAL READS rather than baked-in literals -- the tap COUNT is still fixed at export time, because it comes from the port widths, which ICore resolves once.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | -6.189e16 … 1.049e16 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 5.484 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | 0 … 4 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Transfer_Fcn_Direct_Form_II_Time_Varying.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).