Resettable Delay — Control Systems/Discrete
Control_Systems/Discrete/Resettable_Delay · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Resettable Delay
Control Systems / Discrete
A delay line that can be emptied on demand. Normally it holds the last Delay Length samples and emits the oldest; when the reset port fires, the whole line is cleared back to the Initial Condition and starts refilling from that sample onward.
So a reset tick emits the initial condition, and the input present at the reset reappears Delay Length ticks later – the block forgets its history without losing its place in the schedule.
Ports
- u – the signal to delay, of any size [m,n].
- R – the reset, a scalar [1,1]. How it is read depends on Reset Trigger Type. It resets the whole line, not per entry.
- Output – the delayed signal, the SAME size [m,n] as u.
Parameters
- Delay Length (samples) – how many samples the line holds, at least 1. Defaults to 1, as Simulink's does.
- Initial Condition – a scalar seeding the line, both at the start of the run and after every reset. Defaults to 0.
- Reset Trigger Type – what counts as a reset:
- Rising (default) – the sample the reset goes from zero to nonzero.
- Falling – the sample it goes from nonzero to zero.
- Either – either of those transitions.
- Level – every sample the reset is nonzero, and also the sample it returns to zero. That last part is easy to miss and is not what "level" suggests, but it is what Simulink does – so a pulse of length one resets on two consecutive samples, not one.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each carries the line plus one previous-reset register for the edge detection, and the trigger condition is resolved into a single boolean expression at export time – there is no trigger-type branch left in the generated core.
Simulink bridge
Import and export, mapped to simulink/Discrete/Resettable Delay. "Delay
Length (samples)" to DelayLength, "Initial Condition" to
InitialCondition, "Reset Trigger Type" to
ExternalReset (the four values map 1:1, so the choice is lossless
both ways), and "Sampling Time (s)" to SampleTime as on every
block.
Simulink's block takes its initial condition from a THIRD input port by
default; this one takes it from the dialog, so
InitialConditionSource is always emitted as Dialog and
the exported block has the same two ports this one does.
Notes
- Stateful: the delay line, plus one previous-reset sample.
- Discrete by nature – the line advances one slot per sample.
- A reset clears the line but does not skip the tick. The reset sample is still shifted in, so the block keeps producing one output per sample throughout – unlike Enabled Delay, which freezes.
- Deliberately carries no state space. A delay is transcendental in s, and resetting it on a signal makes the block time-varying as well.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Resettable_Delay |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Resettable_Delay |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Resettable_Delay/ICoreBlock_0_Control_Systems_1_Discrete_2_Resettable_Delay.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Resettable_Delay/ICoreBlock_0_Control_Systems_1_Discrete_2_Resettable_Delay.h |
| default size on canvas | 110 × 80 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | R |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Delay Length (samples) | 1 | DelayLength |
Initial Condition | 0 | InitialCondition |
Reset Trigger Type | Rising%~%Falling%~%Either%~%Level~~Rising | ExternalReset |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Resettable Delay |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | InitialConditionSource = Dialog, DelayLengthSource = Dialog, ShowEnablePort = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Delay Length (samples) | DelayLength | passes through |
Initial Condition | InitialCondition | passes through |
Reset Trigger Type | ExternalReset | Rising → Rising, Falling → Falling, Either → Either, Level → Level |
Caveat (shown to the user): the four reset trigger types map 1:1 onto Simulink's, so the choice is lossless in both directions; note Level also fires on the return to zero
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Resettable Delay — a delay line that can be emptied back to its initial condition on demand Ordinary operation is a fixed shift line: emit the oldest slot, shift the current sample in. When the reset port fires, the WHOLE LINE is cleared to the initial condition FIRST, and the tick then proceeds normally -- so the reset tick emits the initial condition and the line starts refilling from that sample onward.
if (reset fired) hist[*] = initialCondition y = hist[L-1] ; shift ; hist[0] = u
THE FOUR TRIGGER TYPES, verified numerically against Simulink R2026a (length 2, initial condition -1, u = 1..10, R = 0 0 0 1 0 0 1 0 0 0):
Rising : -1 -1 1 -1 -1 4 -1 -1 7 8 fires on 0 -> nonzero Level : -1 -1 1 -1 -1 -1 -1 -1 -1 8 fires while nonzero, AND on nonzero -> 0
Level's extra resets at k = 4 and k = 7 are the whole difference between the two columns, and they are the reason this was measured rather than assumed: "Level" does not mean simply "while the signal is high" -- Simulink also resets on the falling transition out of it. Getting that wrong produces a run that agrees for most samples and diverges at exactly the ticks after a pulse ends, which reads as an off-by-one somewhere else entirely.
The condition is written ONCE, by resetExpr(), and rendered into each target's syntax, so the simulation and all ten exports cannot disagree about what "Level" means.
Discrete by nature: the line advances one slot per SAMPLE.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.7 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 3 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Resettable_Delay.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).