Enabled Delay — Control Systems/Discrete
Control_Systems/Discrete/Enabled_Delay · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Enabled Delay
Control Systems / Discrete
A delay line that only advances while it is enabled:
- Enabled (E ≠ 0) – the block emits the sample from Delay Length enabled ticks ago and shifts the current one in.
- Disabled (E = 0) – the block holds its previous output and the line is frozen: nothing enters, nothing ages.
So the delay is counted in enabled ticks, not in elapsed time. A run that spends half its samples disabled still delays by exactly the configured number of enabled ones, which is what makes this the block for gating a pipeline on and off without losing its contents.
Ports
- u – the signal to delay, of any size [m,n].
- E – the enable, a scalar [1,1]. Any nonzero value enables; exactly zero disables. It gates the whole signal, not per entry.
- Output – the delayed signal, the SAME size [m,n] as u.
Parameters
- Delay Length (samples) – how many enabled ticks the line holds, at least 1. Defaults to 2, as Simulink's does.
- Initial Condition – a scalar seeding the delay LINE, so it is what comes out during the first few enabled ticks. Defaults to 0. Note it does not seed the held output – see the Notes.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each carries the line plus the held-output register as its state, and gates both on the enable exactly as the simulation does. On the three HDL targets the enable becomes a clock-enable on the shift registers, which is what an enabled delay is in hardware anyway.
Simulink bridge
Import and export, mapped to simulink/Discrete/Enabled Delay. "Delay
Length (samples)" to DelayLength, "Initial Condition" to
InitialCondition, and "Sampling Time (s)" to SampleTime
as on every block. Simulink's block is the general Delay configured with an enable
port, so ShowEnablePort is always emitted as on, and the
length and initial condition always come from the dialog rather than from extra
ports – those three are what make it this block, and there is no choice to
offer behind any of them.
Notes
- Stateful: the delay line, plus one held-output register.
- Discrete by nature – the line advances at most one slot per sample.
- The held output starts at zero, not at the Initial Condition. This is deliberate and matches Simulink exactly (verified numerically): the initial condition seeds the delay LINE, while the register a disabled tick re-emits is a separate piece of state that starts at zero. So a block that is disabled at the start of the run emits 0 until it is first enabled, whatever the initial condition says.
- Deliberately carries no state space. A delay is transcendental in s, and gating it on a signal makes the block time-varying as well, so no fixed A/B/C/D describes it.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Enabled_Delay |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Enabled_Delay |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Enabled_Delay/ICoreBlock_0_Control_Systems_1_Discrete_2_Enabled_Delay.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Enabled_Delay/ICoreBlock_0_Control_Systems_1_Discrete_2_Enabled_Delay.h |
| default size on canvas | 110 × 80 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | E |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Delay Length (samples) | 2 | DelayLength |
Initial Condition | 0 | InitialCondition |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Enabled Delay |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | ShowEnablePort = on, DelayLengthSource = Dialog, InitialConditionSource = Dialog |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Delay Length (samples) | DelayLength | passes through |
Initial Condition | InitialCondition | passes through |
Caveat (shown to the user): the delay is counted in ENABLED ticks on both sides; note the held output starts at zero rather than at the initial condition, which is Simulink's behaviour too
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Enabled Delay — a delay line that only advances while its enable port is on ENABLED (E != 0): y = hist[L-1] (the oldest sample), then shift u into the line DISABLED (E == 0): y = the last value emitted; the line is FROZEN
So the delay is measured in ENABLED ticks, not in elapsed samples: three disabled ticks in the middle of a run do not age the line at all.
THE ONE COUNTER-INTUITIVE PART, and the reason this was verified numerically rather than assumed: the held-output register starts at ZERO, not at the Initial Condition. The initial condition seeds the LINE; the register that a disabled tick re-emits is separate and starts at zero. Measured against Simulink R2026a with length 2, initial condition -1, u = 1..10 and E = 0 0 1 1 1 0 0 1 1 1:
out = 0 0 -1 -1 3 3 3 4 5 8 ^^^^ the first two are 0 (disabled, register still at its zero seed) ^^^^^^ then the line's own seed, -1, starts coming out ^ 3 = u[2], the first sample pushed, two enabled ticks later ^^^^^^^ frozen while disabled
Seeding the register with the initial condition instead would have produced -1 -1 for the first two samples and failed parity on exactly two of five hundred points.
Discrete by nature: the line advances at most one slot per SAMPLE.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.6 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 3 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Enabled_Delay.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).