Discrete Time Integrator — Control Systems/Discrete
Control_Systems/Discrete/Discrete_Time_Integrator · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Discrete-Time Integrator
Control Systems / Discrete
Accumulates its input – the discrete counterpart of K/s, computed by one of three rectangle rules:
x[k+1] = x[k] + K·Ts·u[k]
The three methods share that state update exactly and differ only in how much of the current sample reaches the output, which is what makes one of them have direct feedthrough and another not.
Ports
- Input – the signal u being accumulated, of any size [p,m]. Each entry is integrated independently, so a matrix input gives a matrix output of the same shape.
- Output – the accumulated signal y, the SAME size [p,m].
Parameters
- Integration Method – which rectangle rule runs:
- Forward Euler (default) – y[k] = x[k]. The output is the state as it stood BEFORE this sample, so the block has no direct feedthrough and can therefore sit in a feedback loop without creating an algebraic one.
- Backward Euler – y[k] = x[k] + K·Ts·u[k]. The current sample is fully included, so the block has direct feedthrough.
- Trapezoidal – y[k] = x[k] + K·Ts·u[k]/2. Half the current sample is included; the most accurate of the three for a smooth input, and it also has direct feedthrough.
- Gain (K) – a scalar multiplying the input before accumulation. Defaults to 1.
- Initial Condition – a scalar, the state at the start of the run, broadcast to every entry. Defaults to 0.
- Limit Output – off (default) or on. When on, both the output AND the state are clamped to the band below every step. Clamping the state is the part that matters: it is what stops the integrator winding up, so the block leaves the limit as soon as the input changes sign instead of first unwinding an arbitrarily large accumulated value.
- Upper Saturation Limit / Lower Saturation Limit – the band, used only when the limiter is on. Default to inf and −inf, which is the same as no limit.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It multiplies the gain, so it is part of the arithmetic and not merely a schedule.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The method and the gain are resolved into the coefficients at export time, so the generated core carries one multiply-accumulate and no method branch. With the limiter on the core additionally clamps the state and the output, exactly as the simulation does.
Simulink bridge
Import and export, mapped to simulink/Discrete/Discrete-Time
Integrator. "Integration Method" to IntegratorMethod (the three
values map 1:1 onto Simulink's Integration: Forward Euler and its
siblings, so the choice is lossless both ways), "Gain (K)" to
gainval, "Initial Condition" to InitialCondition,
"Limit Output" to LimitOutput, and the two limits to
UpperSaturationLimit / LowerSaturationLimit. "Sampling
Time (s)" crosses as SampleTime, as on every block.
Notes
- Stateful: one accumulator per signal entry.
- Discrete by nature – the state advances once per sample; nothing is integrated by the continuous solver.
- Direct feedthrough depends on the method, which is usually the reason to choose between them: only Forward Euler is free of it, so only Forward Euler can close a loop on its own.
- With the limiter off the block is linear and carries a proper state space, so model reduction can absorb it. With the limiter on the state space still describes the unclamped system, and the clamp sits around it.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Discrete_Time_Integrator |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Time_Integrator |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_Time_Integrator/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Time_Integrator.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_Time_Integrator/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Time_Integrator.h |
| default size on canvas | 110 × 80 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Integration Method | Forward Euler%~%Backward Euler%~%Trapezoidal~~Forward Euler | IntegratorMethod |
Gain (K) | 1 | gainval |
Initial Condition | 0 | InitialCondition |
Limit Output | off%~%on~~off | LimitOutput |
Upper Saturation Limit | inf | UpperSaturationLimit |
Lower Saturation Limit | -inf | LowerSaturationLimit |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Discrete-Time Integrator |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Integration Method | IntegratorMethod | Forward Euler → Integration: Forward Euler, Backward Euler → Integration: Backward Euler, Trapezoidal → Integration: Trapezoidal |
Gain (K) | gainval | passes through |
Initial Condition | InitialCondition | passes through |
Limit Output | LimitOutput | off → off, on → on |
Upper Saturation Limit | UpperSaturationLimit | passes through |
Lower Saturation Limit | LowerSaturationLimit | passes through |
Caveat (shown to the user): the three integration methods map 1:1 onto Simulink's, so the choice is lossless in both directions
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Discrete-Time Integrator — an accumulator with three rectangle rules and an optional limiter All three integration methods share the SAME A and B and differ only in D:
A = [1] B = [K*Ts] C = [1] Forward Euler D = [0] y[k] = x[k] (no direct feedthrough) Backward Euler D = [K*Ts] y[k] = x[k] + K*Ts*u[k] Trapezoidal D = [K*Ts/2] y[k] = x[k] + K*Ts/2*u[k] x[k+1] = x[k] + K*Ts*u[k] (the same for all three)
Verified against Simulink R2026a, K = 2, Ts = 1, x0 = 0.5, u = 1..10: Forward 0.5 2.5 6.5 12.5 20.5 ... Backward 2.5 6.5 12.5 20.5 30.5 ... Trapezoidal 1.5 4.5 9.5 16.5 25.5 ...
THE LIMITER IS WHERE THIS STOPS BEING LINEAR. With it on, BOTH the output and the state are clamped every step -- measured on the same rig with the band [-3, 12]: 0.5 2.5 6.5 12 12 12 ... (unlimited would be 0.5 2.5 6.5 12.5 20.5 30.5) The state saturating is what stops the integrator winding up: once x reaches the limit it stays there, so the block comes off the limit the moment the input changes sign rather than after unwinding an arbitrarily large accumulated value.
So the block takes both paths deliberately:
- LIMITER OFF -- delegate every generator to ICoreDiscreteLinearBlock's shared ones, so
the common case is bit-identical to the other linear Discrete blocks and gets their ten backends for free.
- LIMITER ON -- the block emits its own bodies, because a clamp is not expressible as
A/B/C/D and wrapping the shared emission textually would be a worse lie than writing it out. n = 1 here, so each one is a short loop over the signal's entries.
buildRealization() reports the UNCLAMPED system either way: the clamp is a saturation around that system, not a different linear system, and reporting it is what keeps the block's state space meaningful to linear analysis.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0.1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 16.53 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.002431 … 0.9987 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -0.35 … 2.1 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Discrete_Time_Integrator.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).