Discrete PID Controller — Control Systems/Discrete
Control_Systems/Discrete/Discrete_PID_Controller · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Discrete PID Controller
Control Systems / Discrete
A discrete-time PID controller with a filtered derivative. It takes the error signal e and produces the control signal u, updating once per sample:
Parallel: u = P·e + I·Fi(z)·e +
D·N/(1 + N·Fd(z))·e
Ideal: u = P·( e + I·Fi(z)·e +
D·N/(1 + N·Fd(z))·e )
Fi and Fd are the discrete accumulators chosen by the two method parameters. This is the sampled counterpart of the continuous PID Controller; the derivative is never taken bare, so the controller stays proper and has a two-state realization.
Ports
- Input – the error e, of any size [p,m].
- Output – the control signal u, of the same size.
The controller is SISO, but it is applied independently to every entry of the input signal, each entry carrying its own two states.
Parameters
- Proportional (P) – the proportional gain, a scalar.
- Integral (I) – the integral gain, a scalar. Zero removes the integral action.
- Derivative (D) – the derivative gain, a scalar. Zero removes the derivative action, whatever N is.
- Filter Coefficient (N) – the derivative filter bandwidth, a non-negative scalar. A large N tracks the ideal derivative closely and a small one smooths it heavily. Zero removes the derivative action outright.
- Controller Form – how P enters the sum:
- Parallel – P, I and D are independent gains on the three branches.
- Ideal – P multiplies the whole controller, so it scales the integral and derivative action too.
- Integrator Method – which accumulator realizes the integral
branch:
- Forward Euler – Ts/(z−1). The output does not depend on the current error, so the branch adds no direct feedthrough.
- Backward Euler – Ts·z/(z−1).
- Trapezoidal – (Ts/2)·(z+1)/(z−1), the most accurate of the three for a given rate.
- Filter Method – the same three choices for the derivative filter, picked independently of the integrator's.
- Initial Condition (Integrator) – the integrator accumulator at the start of the run, a scalar used for every entry. The I gain sits before the integrator, so this is the initial value of the integral term, not of the accumulated error.
- Initial Condition (Filter) – the derivative filter's accumulator at the start of the run, a scalar used for every entry. It is expressed exactly as Simulink expresses it, which for the Backward Euler and Trapezoidal filter methods is a differently scaled state than the one this block steps – the block converts it, so the same number means the same thing on both sides.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is not merely a schedule here: it is the Ts in both accumulators, so changing it changes the controller.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Unlike the continuous PID, nothing has to be discretized at export time – the block is already a difference equation, so the generated core runs the identical recursion the in-app simulation does.
P, I, D and N are not tunable on the generated core: the two method choices and the sampling period mix them into the A/B/C/D that is embedded, so retuning would mean re-deriving them on the target. Change them here and export again. The two initial conditions are baked in as the state seed for the same reason.
Simulink bridge
Import and export, mapped to
simulink/Discrete/Discrete PID Controller.
"Proportional (P)" to P, "Integral (I)" to I,
"Derivative (D)" to D, "Filter Coefficient (N)" to N,
"Controller Form" to Form, "Integrator Method" to
IntegratorMethod, "Filter Method" to FilterMethod (all
three are 1:1 and therefore lossless pairs), "Initial Condition (Integrator)" to
InitialConditionForIntegrator, "Initial Condition (Filter)" to
InitialConditionForFilter, and "Sampling Time (s)" to
SampleTime, as on every block.
Three Simulink parameters are always implied rather than offered as a choice:
Controller = PID, TimeDomain =
Discrete-time and UseFilter = on. The full PID structure
covers Simulink's PI, PD, P and I controllers numerically – set D to zero for
PI, I to zero for PD – so nothing is lost by always emitting it.
What does not cross: output saturation with anti-windup
(LimitOutput), external reset (ExternalReset), external
initial conditions and tracking mode all add input ports in Simulink, and no config
value here can add or remove a port. An unfiltered derivative
(UseFilter = off) does not cross either: it is a bare
difference, and Discrete Derivative is the block for that.
Notes
- Discrete only, and stateful: two accumulators per input entry.
- Being linear, the block is directly usable by the model reduction and linear-analysis commands.
- Integrator wind-up is not limited. With no output saturation to unwind
against, a sustained error accumulates without bound – the same behaviour
Simulink's block has with
LimitOutputoff.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Discrete_PID_Controller |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_PID_Controller |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_PID_Controller/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_PID_Controller.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_PID_Controller/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_PID_Controller.h |
| default size on canvas | 120 × 85 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Proportional (P) | 1 | P |
Integral (I) | 1 | I |
Derivative (D) | 0 | D |
Filter Coefficient (N) | 100 | N |
Controller Form | Parallel%~%Ideal~~Parallel | Form |
Integrator Method | Forward Euler%~%Backward Euler%~%Trapezoidal~~Forward Euler | IntegratorMethod |
Filter Method | Forward Euler%~%Backward Euler%~%Trapezoidal~~Forward Euler | FilterMethod |
Initial Condition (Integrator) | 0 | InitialConditionForIntegrator |
Initial Condition (Filter) | 0 | InitialConditionForFilter |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Discrete PID Controller |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | Controller = PID, TimeDomain = Discrete-time, UseFilter = on |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Proportional (P) | P | passes through |
Integral (I) | I | passes through |
Derivative (D) | D | passes through |
Filter Coefficient (N) | N | passes through |
Controller Form | Form | Parallel → Parallel, Ideal → Ideal |
Integrator Method | IntegratorMethod | Forward Euler → Forward Euler, Backward Euler → Backward Euler, Trapezoidal → Trapezoidal |
Filter Method | FilterMethod | Forward Euler → Forward Euler, Backward Euler → Backward Euler, Trapezoidal → Trapezoidal |
Initial Condition (Integrator) | InitialConditionForIntegrator | passes through |
Initial Condition (Filter) | InitialConditionForFilter | passes through |
Caveat (shown to the user): output saturation/anti-windup, external reset, external initial conditions and tracking mode are not supported (each adds an input port in Simulink); the derivative is always filtered, since an unfiltered one is a bare difference and Discrete Derivative is the block for that
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Discrete PID Controller block — filtered-derivative PID, element-wise The sampled counterpart of Control_Systems/Continues/PID_Controller. See the header for the A/B/C/D and for the two method constants that generate them. Everything below the matrices comes from ICoreDiscreteLinearBlockBase.
THE REALIZATION IS SIMULINK'S, not an arbitrary equivalent one: the I gain sits BEFORE the integrator and the derivative filter is a feedback loop around a second accumulator, which is what lets "Initial Condition (Integrator)" map across untouched. The FILTER initial condition needs one conversion, measured against Simulink rather than assumed — see filterInitialConditionScale() below.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 22.33 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.5744 … 1.57 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 4.8 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Discrete_PID_Controller.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).