Generated reference › Discrete PID Controller 2DOF — Control Systems/Discrete
kind: generated#block#control-systems-discrete

Discrete PID Controller 2DOF — Control Systems/Discrete

PID z 2-DOF

Control_Systems/Discrete/Discrete_PID_Controller_2DOF · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Discrete PID Controller (2DOF)

Control Systems / Discrete

A two-degree-of-freedom discrete-time PID controller. It takes the reference r and the measurement y on separate input ports rather than a pre-formed error, which is what lets the setpoint weights b and c route the reference into the proportional and derivative branches independently of the integral one:

Parallel:  u = P·(b·r − y) + I·Fi(z)·(r − y) + D·N/(1 + N·Fd(z))·(c·r − y)
Ideal:     u = P·[ the same three terms ]

Fi and Fd are the discrete accumulators chosen by the two method parameters. Setting b = c = 1 collapses the block to the one-degree-of-freedom Discrete PID Controller. The point of it is b < 1, which softens the proportional kick on a setpoint step without touching the disturbance response, and c = 0, which removes derivative kick entirely.

Ports

  • r – the reference (setpoint), of any size [p,m]. It reaches the proportional branch weighted by b and the derivative branch weighted by c.
  • y – the measurement, the same size as r. It enters every branch unweighted.
  • u – the control signal, the same size again.

The controller is two-input/one-output, but it is applied independently to every entry of the signals, each entry carrying its own two states.

Parameters

  • Proportional (P) – the proportional gain, a scalar.
  • Integral (I) – the integral gain, a scalar. Zero removes the integral action.
  • Derivative (D) – the derivative gain, a scalar. Zero removes the derivative action, whatever N and c are.
  • Filter Coefficient (N) – the derivative filter bandwidth, a non-negative scalar. Zero removes the derivative action outright.
  • Setpoint Weight (b) – how much of the reference reaches the proportional branch. One gives the ordinary error P·(r − y); zero makes the proportional action respond to the measurement alone.
  • Setpoint Weight (c) – the same for the derivative branch. Zero is the common choice, and removes derivative kick on a setpoint step.
  • Controller Form – how P enters the sum:
    • Parallel – P, I and D are independent gains on the three branches.
    • Ideal – P multiplies the whole controller, including the setpoint-weighted proportional term, so it scales the integral and derivative action too.
  • Integrator Method – which accumulator realizes the integral branch:
    • Forward Euler – Ts/(z−1). The output does not depend on the current error, so the branch adds no direct feedthrough.
    • Backward Euler – Ts·z/(z−1).
    • Trapezoidal – (Ts/2)·(z+1)/(z−1), the most accurate of the three for a given rate.
  • Filter Method – the same three choices for the derivative filter, picked independently of the integrator's.
  • Initial Condition (Integrator) – the integrator accumulator at the start of the run, a scalar used for every entry. The I gain sits before the integrator, so this is the initial value of the integral term.
  • Initial Condition (Filter) – the derivative filter's accumulator at the start of the run, a scalar used for every entry. It is expressed exactly as Simulink expresses it, which for the Backward Euler and Trapezoidal filter methods is a differently scaled state than the one this block steps – the block converts it, so the same number means the same thing on both sides.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is not merely a schedule here: it is the Ts in both accumulators, so changing it changes the controller.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Nothing has to be discretized at export time – the block is already a difference equation, so the generated core runs the identical recursion the in-app simulation does.

P, I, D, N, b and c are not tunable on the generated core: the two method choices and the sampling period mix them into the A/B/C/D that is embedded. Change them here and export again. The two initial conditions are baked in as the state seed for the same reason.

Simulink bridge

Import and export, mapped to simulink/Discrete/Discrete PID Controller (2DOF). "Proportional (P)" to P, "Integral (I)" to I, "Derivative (D)" to D, "Filter Coefficient (N)" to N, "Setpoint Weight (b)" to b, "Setpoint Weight (c)" to c, "Controller Form" to Form, "Integrator Method" to IntegratorMethod, "Filter Method" to FilterMethod (all three are 1:1 and therefore lossless pairs), "Initial Condition (Integrator)" to InitialConditionForIntegrator, "Initial Condition (Filter)" to InitialConditionForFilter, and "Sampling Time (s)" to SampleTime, as on every block.

Three Simulink parameters are always implied rather than offered as a choice: Controller = PID, TimeDomain = Discrete-time and UseFilter = on.

What does not cross: output saturation with anti-windup (LimitOutput), external reset (ExternalReset), external initial conditions and tracking mode all add input ports in Simulink, and no config value here can add or remove a port.

Notes

  • Discrete only, and stateful: two accumulators per input entry.
  • Being linear, the block is directly usable by the model reduction and linear-analysis commands.
  • Integrator wind-up is not limited, as on the one-degree-of-freedom block.

Code facts#

FactValue
registered typeControl_Systems/Discrete/Discrete_PID_Controller_2DOF
familyControl_Systems/Discrete
solver environment classICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_PID_Controller_2DOF
sourcesrc/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_PID_Controller_2DOF/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_PID_Controller_2DOF.cpp
headersrc/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_PID_Controller_2DOF/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_PID_Controller_2DOF.h
default size on canvas130 × 95 px
ports at insert2 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDoubler
2inICoreDoubley
3outICoreDoubleu

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Proportional (P)1P
Integral (I)1I
Derivative (D)0D
Filter Coefficient (N)100N
Setpoint Weight (b)1b
Setpoint Weight (c)1c
Controller FormParallel%~%Ideal~~ParallelForm
Integrator MethodForward Euler%~%Backward Euler%~%Trapezoidal~~Forward EulerIntegratorMethod
Filter MethodForward Euler%~%Backward Euler%~%Trapezoidal~~Forward EulerFilterMethod
Initial Condition (Integrator)0InitialConditionForIntegrator
Initial Condition (Filter)0InitialConditionForFilter

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::Both
Simulink pathsimulink/Discrete/Discrete PID Controller (2DOF)
port-count rulePortsParam::None
SampleTime parameteryes
always setController = PID, TimeDomain = Discrete-time, UseFilter = on
ICore configSimulink parameterValue translation
Proportional (P)Ppasses through
Integral (I)Ipasses through
Derivative (D)Dpasses through
Filter Coefficient (N)Npasses through
Setpoint Weight (b)bpasses through
Setpoint Weight (c)cpasses through
Controller FormFormParallelParallel, IdealIdeal
Integrator MethodIntegratorMethodForward EulerForward Euler, Backward EulerBackward Euler, TrapezoidalTrapezoidal
Filter MethodFilterMethodForward EulerForward Euler, Backward EulerBackward Euler, TrapezoidalTrapezoidal
Initial Condition (Integrator)InitialConditionForIntegratorpasses through
Initial Condition (Filter)InitialConditionForFilterpasses through

Caveat (shown to the user): output saturation/anti-windup, external reset, external initial conditions and tracking mode are not supported (each adds an input port in Simulink); the derivative is always filtered

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Discrete PID Controller (2DOF) block — setpoint-weighted PID, element-wise The sampled counterpart of Control_Systems/Continues/PID_Controller_2DOF, and the 1DOF discrete controller with the two weighted errors substituted. See the header for the A/B/C/D. Everything below the matrices comes from ICoreDiscreteLinearBlockBase.

Sample results#

Discrete PID Controller 2DOF — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sampleDiscrete PID Controller 2DOF — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample-202012345t (s)in ICoreDouble-Out-0in ICoreDouble-Out-0out ICoreDouble-Out-0
tin ICoreDouble-Out-0in ICoreDouble-Out-0out ICoreDouble-Out-0
0-2-20
0.40.50.50
0.8-2-22.776e-17
1.20.50.52.776e-17
1.6-2-25.551e-17
20.50.55.551e-17
2.4-2-28.327e-17
2.80.50.58.327e-17
3.2-2-21.11e-16
3.60.50.51.11e-16
4-2-21.388e-16
4.40.50.51.388e-16
4.8-2-21.665e-16
5.20.50.51.665e-16

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

StimulusWhat it isOutput range
impulseImpulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)0 … 0
rampRamp: slope 1 from t = 0-3.331e-17 … 1.743e-16
sineSine Wave: amplitude 1, 2 rad/s, no phase, no bias0 … 3.206e-17
stepStep: 0 -> 1 at t = 1 s0 … 0

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Discrete_PID_Controller_2DOF.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).