Discrete Filter — Control Systems/Discrete
Control_Systems/Discrete/Discrete_Filter · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Discrete Filter
Control Systems / Discrete
An IIR filter whose coefficients are given in ascending powers of 1/z:
H(z) = (b0 + b1z−1 + … + bMz−M) / (a0 + a1z−1 + … + aNz−N)
realized as the difference equation y[k] = ( ∑ bi·u[k−i] − ∑i≥1 ai·y[k−i] ) / a0.
This is the one thing that separates it from Discrete Transfer
Function, which takes the same two vectors in descending powers of z.
The pair numerator [1], denominator [1 -0.5] means
y[k] = u[k] + 0.5·y[k−1] here, but
y[k] = u[k−1] + 0.5·y[k−1] there – a whole sample of delay
apart, from input that looks identical. Reach for this block when your
coefficients came from a filter designer, and for the other when they came from a
z-domain transfer function.
Ports
- Input – the signal to filter, of any size [p,m].
- Output – the filtered signal, of the same size.
The filter is SISO, but it is applied independently to every entry of the input signal, each entry carrying its own state.
Parameters
- Numerator – b0…bM, a vector in ascending powers of 1/z. A single value makes an all-pole filter.
- Denominator – a0…aN, likewise. a0 must not be zero; it need not be one, and the whole filter is normalized by it. A single value makes the filter FIR, and Discrete FIR Filter is then the more direct block.
- Initial States – the filter's internal state at the start of the run. A scalar seeds every state; a vector of length n = max(M, N) seeds them individually, newest first.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The coefficients are normalized by a0 and baked into the generated recursion rather than exposed as tunable parameters: they also fix how many state words the core carries, so retuning them on the target is not possible. Change them here and export again.
Simulink bridge
Import and export, mapped to simulink/Discrete/Discrete Filter.
"Numerator" to Numerator, "Denominator" to Denominator,
"Initial States" to InitialStates, and "Sampling Time (s)" to
SampleTime, as on every block.
Three Simulink parameters are always implied rather than offered as a choice:
FilterStructure = Direct form II, which is the structure this
block realizes and therefore what makes the initial states mean the same thing on
both sides, and NumeratorSource / DenominatorSource =
Dialog, since the coefficients come from the config here and never from a
port.
What does not cross: coefficients or initial states arriving on a port, and external reset, all add input ports in Simulink, and no config value here can add or remove a port. Choosing a different Simulink filter structure does not cross either – the alternatives define their states differently, so the initial states would no longer mean the same thing.
Notes
- Discrete only, and stateful: n = max(M, N) past values per entry.
- Being linear, the block is directly usable by the model reduction and linear-analysis commands.
- Stability is the user's to check: poles outside the unit circle make the output grow without bound, and the block does not stop the run for it.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Discrete_Filter |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Filter |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_Filter/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Filter.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Discrete_Filter/ICoreBlock_0_Control_Systems_1_Discrete_2_Discrete_Filter.h |
| default size on canvas | 130 × 90 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Numerator | [1] | Numerator |
Denominator | [1 0.5] | Denominator |
Initial States | 0 | InitialStates |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Discrete Filter |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | FilterStructure = Direct form II, NumeratorSource = Dialog, DenominatorSource = Dialog |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Numerator | Numerator | passes through |
Denominator | Denominator | passes through |
Initial States | InitialStates | passes through |
Caveat (shown to the user): coefficients or initial states arriving on a port, and external reset, are not supported (each adds an input port in Simulink); the filter structure is always Direct form II, since the alternatives define their states differently and the initial states would stop meaning the same thing
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Discrete Filter block — IIR in ascending powers of 1/z, element-wise Direct form II, so the states are the internal w sequence Simulink's "Initial states" names and they seed 1:1. See the header for the coefficient convention (the one thing that separates this block from Discrete Transfer Function) and the A/B/C/D. Everything below the matrices comes from ICoreDiscreteLinearBlockBase.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -0.5 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 3.889 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.6689 … 0.6696 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -3.106 … 2.212 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Discrete_Filter.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).