Difference — Control Systems/Discrete
Control_Systems/Discrete/Difference · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Difference
Control Systems / Discrete
The change in the input from one sample to the next:
y[k] = u[k] − u[k−1]
On the very first sample there is no previous input to subtract, so the block uses the configured initial condition in its place. In transfer-function terms it is 1 − z−1.
This is a difference, not a derivative: it is not divided by the sampling period, so its magnitude depends on how fast the block is stepped. Use Discrete Derivative for the rate of change in units per second.
Ports
- Input – the signal to difference, of any size [p,m].
- Output – the sample-to-sample change, of the same size.
The difference is scalar, but it is applied independently to every entry of the input signal, each entry remembering its own previous value.
Parameters
- Initial Condition (Previous Input) – the value standing in for u[−1] on the first sample, a scalar applied to every entry. Leave it at zero and the first output is simply the first input.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The initial condition is baked in as the state seed rather than exposed as a tunable parameter, since it only affects the first sample of a run.
Simulink bridge
Import and export, mapped to simulink/Discrete/Difference.
"Initial Condition (Previous Input)" to ICPrevInput.
"Sampling Time (s)" does not cross, unusually: Simulink's Difference is
a masked subsystem with no SampleTime parameter at all, so the
rate stays on the ICore side and a block configured with an explicit positive rate
reports that it did not carry over. In Simulink the block simply inherits the rate
of whatever drives it.
Notes
- Discrete only, and stateful: one past sample per entry.
- Being linear, the block is directly usable by the model reduction and linear-analysis commands.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Difference |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Difference |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Difference/ICoreBlock_0_Control_Systems_1_Discrete_2_Difference.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Difference/ICoreBlock_0_Control_Systems_1_Discrete_2_Difference.h |
| default size on canvas | 100 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Initial Condition (Previous Input) | 0 | ICPrevInput |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Difference |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Initial Condition (Previous Input) | ICPrevInput | passes through |
Caveat (shown to the user): the sampling time does not cross: Simulink's Difference is a masked subsystem with no SampleTime parameter, and inherits the rate of whatever drives it
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Difference block — y[k] = u[k] - u[k-1], element-wise One state, and it IS the previous input, which is what makes Simulink's initial condition carry over without rescaling. See the header for the A/B/C/D. Everything below the matrices comes from ICoreDiscreteLinearBlockBase.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | -1 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 0.1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.1995 … 0.1996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -5 … 1 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Difference.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).