Delay — Control Systems/Discrete
Control_Systems/Discrete/Delay · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Delay
Control Systems / Discrete
Holds the input back by a whole number of samples:
y[k] = u[k − L]
where L is the delay length. For the first L samples of a run there is nothing to pass on yet, so the block emits the initial condition instead; from sample L onwards it emits the input as it stood L samples earlier. In transfer-function terms it is z−L.
Ports
- Input – the signal to delay, of any size [p,m].
- Output – the same signal L samples later, of the same size.
The delay line is scalar, but it is applied independently to every entry of the input signal, each entry carrying its own L samples in flight.
Parameters
- Delay Length (samples) – a non-negative whole number, counted in SAMPLES rather than seconds: the delay in time is this value times the block's sampling period. Zero makes the block pass its input straight through.
- Initial Condition – the value the output takes for the first L samples, a scalar applied to every entry and to every sample in flight.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The delay length is structural rather than tunable: it fixes how many state words the generated core carries, so it is baked in at export time and cannot be retuned on the target. Change it here and export again.
The three HDL targets emit the shift register unrolled, so a long delay on a large signal is a large entity – the state word count is L×p×m.
Simulink bridge
Import and export, mapped to simulink/Discrete/Delay.
"Delay Length (samples)" to DelayLength, "Initial Condition" to
InitialCondition, and "Sampling Time (s)" to SampleTime,
as on every block. Both sources are always Dialog: this block takes its
length and its initial value from its own config, never from a port.
What does not cross: an external delay length, an external initial condition, the enable port and external reset all add input ports in Simulink, and no config value here can add or remove a port.
Notes
- Discrete only, and stateful: L samples per entry.
- Being linear, the block is directly usable by the model reduction and linear-analysis commands.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discrete/Delay |
| family | Control_Systems/Discrete |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discrete_2_Delay |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Delay/ICoreBlock_0_Control_Systems_1_Discrete_2_Delay.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discrete/Delay/ICoreBlock_0_Control_Systems_1_Discrete_2_Delay.h |
| default size on canvas | 110 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Delay Length (samples) | 2 | DelayLength |
Initial Condition | 0 | InitialCondition |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discrete/Delay |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | DelayLengthSource = Dialog, InitialConditionSource = Dialog |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Delay Length (samples) | DelayLength | passes through |
Initial Condition | InitialCondition | passes through |
Caveat (shown to the user): an external delay length, an external initial condition, the enable port and external reset are not supported (each adds an input port in Simulink)
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Delay block — a whole-sample shift register, element-wise y[k] = u[k - L]. The L states ARE the L samples still in flight, which is what makes Simulink's scalar InitialCondition seed them without rescaling. See the header for the A/B/C/D. Everything below the matrices — the ten code generators, the per-entry state plumbing, the two compute_*_discrete bodies — comes from ICoreDiscreteLinearBlockBase.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.6 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 3 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discrete__Delay.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).