Variable Pulse Generator — Control Systems/Discontinuities

Variable Pulse Generator

Control Systems / Discontinuities

A pulse train whose duty cycle and period both arrive on input ports – the PWM block with its period freed from the configuration. Both inputs are read once at the start of each period and held, with nPeriod = round(T / Ts) samples in the cycle:

• the output is 1 for the first floor(duty · nPeriod) samples of the period and 0 for the rest;
• the phase then wraps against the latched period, so a period that changes mid-cycle takes effect only at the next boundary – 0.2 s followed by 0.3 s gives cycles of 0.2, 0.2, then 0.3.

A duty outside [0,1] is clamped. Applied entry by entry, and here that means each entry runs its own independent generator, with its own phase and its own period.

Ports

• Input 1 – dc – the duty cycle, a fraction in [0,1]. Its size is the block's output size.
• Input 2 – T – the period, in seconds. Rounded to a whole number of samples, and never below one sample.
• Output – the pulse train, of the SAME size as dc, carrying 1 or 0 per entry.

Both inputs must carry the same signal size; a mismatch is reported and the run is stopped rather than broadcast.

Parameters

• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It converts the period signal into a sample count and is the resolution of the pulse: the high time can only ever be a whole number of samples.

There are no other parameters: everything this block needs comes in on a port.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Only the sampling period is baked in as a constant; the duty and the period are read from signals. The exported state is the phase counter plus the latched period and duty, one set per entry. Every target evaluates the same phase + 1 ≤ duty · nPeriod test, so none can drift from the others on a rounding convention – on the three HDL targets that comparison is done entirely in Q-format, with the phase scaled up rather than the product scaled down, so no division is ever emitted.

Turning the period into a sample count in hardware needs a fixed-point to whole-number conversion, which the generated Fx package provides as fx_to_int – an arithmetic shift by the fraction width, i.e. floor(), the same rounding the software targets get.

One caveat specific to the HDL targets. The period arrives as a signal, so an HDL port delivers it already quantized to the Q16.16 format. One quantum is about 1.5×10⁻⁵, which at a 0.01 s rate is 1.5×10⁻³ of a sample – enough to move round(T / Ts) by a whole sample if the period lands within that of a half-sample boundary. That would not shift the output slightly; it would change the cycle length, and the core would then run out of step with the reference for the rest of the run. Drive this block with periods that are clean multiples of the sampling time and the three HDL exports are bit-exact. PWM has no such caveat at all, because its period is a configuration value resolved to an exact sample count at export time.

Simulink bridge

Import and export, mapped to simulink/Discontinuities/Variable Pulse Generator. There are no parameters to map in either direction; the block's whole configuration is its wiring, and the dc, T port order is what has to line up. "Sampling Time (s)" goes to SampleTime, as on every block. Two Simulink parameters are always written and have no ICore counterpart: RunAtFixedTimeIntervals is fixed to on, without which the Simulink block refuses to run under a fixed-step solver at all, and AllowZeroPulseWidth is fixed to on, because ICore has nothing to reject – a zero duty simply holds the output low for the period, where Simulink would otherwise stop the run with an error.

Notes

• Stateful: a phase counter, a latched period and a latched duty per entry.
• Discrete by nature – the output is a function of the sample index, so the block always runs at its own rate rather than being pushed through a continuous solver's stages.
• Both inputs are read only on the sample that opens a period. Feeding either a signal that changes faster than the period is not an error, but everything between boundaries is discarded.
• A period below one sample is raised to one sample rather than stalling the generator.
• Not linear, and so deliberately carries no state space.