Rate Limiter Dynamic — Control Systems/Discontinuities

Rate Limiter Dynamic

Control Systems / Discontinuities

Caps how fast the output may follow the input, exactly like Rate Limiter, except that the slew band arrives on input ports instead of sitting in the configuration. With y the previously held output and dt the block's sampling period:

and d = u − y the step the input is asking for:

• d > up·dt → y = y + up·dt
• d < lo·dt → y = y + lo·dt
• otherwise → y = u, the demanded step already fits

Because the limits are signals they may move while the model runs, which is what the block is for – a slew schedule, a rate envelope that depends on operating point. Applied entry by entry.

Ports

• Input 1 – up – the rising rate limit, in units per second.
• Input 2 – u – the demanded signal. Its size is the block's output size.
• Input 3 – lo – the falling rate limit, in units per second, and therefore negative.
• Output – the rate-limited signal y, of the SAME size as u.

The port order up, u, lo is Simulink's for this block, top to bottom. All three inputs must carry the same signal size; a mismatch is reported and the run is stopped rather than broadcast.

Parameters

• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It converts both limit signals from rates into per-sample steps, so it is part of the arithmetic and not just the schedule. ICore-side only – see the bridge note below.

There are no other parameters: everything this block needs comes in on a port. In particular there is no initial condition: the first sample passes straight through and seeds the held output, so limiting begins on the second sample. That is the Simulink block's own behaviour, and it differs from the fixed-parameter Rate Limiter, which clamps its very first sample against its configured initial condition.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Only one constant is baked in – the sampling period that turns the limit signals into steps – because everything else is read from a signal at every step. The exported state is the held output itself, one value per entry, seeded from the first input sample.

The three HDL targets carry the recursion in simulation-only real arithmetic, quantizing only on the way out to the signal port, as the Sine Wave block does. That is forced by the block's shape rather than chosen for convenience: because the limits arrive as signals, the per-sample step has to be formed at run time as up · dt, and a sampling period of 0.01 s is not representable in the Q16.16 port format – it comes out as 0.0099945, a systematic error of 5.5×10⁻⁴. In a block that accumulates its own output, that bias integrates into a visible drift instead of staying at the port quantum. The fixed-parameter Rate Limiter has no such problem and stays fully fixed-point, because its step is a constant folded at export time and dt never appears in the generated core.

Simulink bridge

Import and export, mapped to simulink/Discontinuities/Rate Limiter Dynamic. There are no parameters to map in either direction; the block's whole configuration is its wiring, and the up, u, lo port order is what has to line up. "Sampling Time (s)" does NOT cross: this Simulink block has no SampleTime parameter, so the rate stays on the ICore side and an explicitly set one is reported rather than written. That matters more here than on the algebraic dynamic blocks, because the sampling period scales the slew step – two sides stepping differently produce genuinely different outputs.

Notes

• Stateful, unlike Saturation Dynamic and Dead Zone Dynamic, which are algebraic: this block remembers where its output got to.
• The first sample is not limited: it seeds the held output. A rig that compares only later samples would never notice a core that got this wrong.
• Discrete by nature – the band is a step per sample, so the block always runs at its own rate rather than being pushed through a continuous solver's stages.
• An inverted band (lo·dt above up·dt) is NOT an error here – the limits are signals, so it can happen for a single step. The step is then tested against the upper bound first and the lower bound only if that did not fire, so the upper bound wins. Every one of the ten targets resolves it the same way.
• Not linear, and so deliberately carries no state space.