Quantizer — Control Systems/Discontinuities
Control_Systems/Discontinuities/Quantizer · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Quantizer
Control Systems / Discontinuities
Snaps the input onto a lattice of equally spaced levels: y = q · round(u / q), where q is the quantization interval. The result is the staircase an ADC or a fixed-resolution sensor produces. Applied entry by entry, so a matrix signal is quantized element for element.
Ports
- Input – the signal u, of any size [m,n].
- Output – the quantized signal y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- Quantization Interval – scalar, the spacing q between levels. Defaults to 0.5, as in Simulink. It must be strictly positive; a zero or negative interval is reported and the run is stopped rather than dividing by zero.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The interval is baked in as a constant at export time.
The rounding is half away from zero, as in MATLAB. Not every language
agrees by default – numpy rounds halves to even, and Java's
Math.round is a floor on a long – so those two targets emit an
explicit truncation form rather than the built-in, and every target lands on the
same level.
The three HDL targets carry no divider, so they multiply by the constant 1/q and round by shifting. That is round-half-up, which parts from half-away-from-zero only when a sample lands exactly on a half-level.
Simulink bridge
Import and export, mapped to simulink/Discontinuities/Quantizer.
"Quantization Interval" to QuantizationInterval as a plain
pass-through value, so the round trip is lossless. "Sampling Time (s)" goes to
SampleTime, as on every block.
Notes
- Algebraic, with no state.
- Zero is always a level, and the lattice is symmetric about it.
- Not linear, and so deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing the staircase.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Discontinuities/Quantizer |
| family | Control_Systems/Discontinuities |
| solver environment class | ICoreBlock_0_Control_Systems_1_Discontinuities_2_Quantizer |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Quantizer/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Quantizer.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Quantizer/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Quantizer.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Quantization Interval | 0.5 | QuantizationInterval |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Discontinuities/Quantizer |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Quantization Interval | QuantizationInterval | passes through |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Quantizer block — snap to a lattice of step q y = q * round(u/q), entry by entry. Algebraic and stateless, no state space (see header).
Rounding convention: HALF AWAY FROM ZERO, matching MATLAB/Simulink. Python and Java get an explicit form because np.round is banker's and Math.round is floor(x+0.5) on a long. The HDL targets have no divider: they multiply by the constant 1/q and round by shifting.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -2 |
| 0.4 | 0.5 | 0.5 |
| 0.8 | -2 | -2 |
| 1.2 | 0.5 | 0.5 |
| 1.6 | -2 | -2 |
| 2 | 0.5 | 0.5 |
| 2.4 | -2 | -2 |
| 2.8 | 0.5 | 0.5 |
| 3.2 | -2 | -2 |
| 3.6 | 0.5 | 0.5 |
| 4 | -2 | -2 |
| 4.4 | 0.5 | 0.5 |
| 4.8 | -2 | -2 |
| 5.2 | 0.5 | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 6 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 1 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discontinuities__Quantizer.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).