PWM — Control Systems/Discontinuities

PWM

Control Systems / Discontinuities

A pulse-width modulator: a square wave of fixed period whose high fraction is the duty cycle arriving on the input port. Everything is counted in whole samples at the block's own rate, with nPeriod = Period / Ts samples per period:

• the duty is sampled once at the start of each period and held – a duty that changes mid-period has no effect until the next boundary;
• the output is 1 for the first floor(duty · nPeriod) samples of the period and 0 for the rest.

So a duty of 0.25 over a 50-sample period gives 12 high samples, not 12.5 and not 13. A duty outside [0,1] is clamped. Applied entry by entry: a matrix duty gives a matrix of independently modulated pulse trains sharing one clock.

Ports

• Input – the duty cycle dc, a fraction in [0,1], of any size [m,n]. Values outside the range are clamped rather than rejected.
• Output – the pulse train, of the SAME size [m,n], carrying 1 or 0 per entry. The block never reshapes a signal.

Parameters

• Period (s) – scalar, the length of one full cycle. Defaults to 1, as in Simulink. Must be positive and a whole number of sampling periods; anything else is reported rather than silently rounded.
• Initial Delay (s) – scalar, how long the output is held low before the first pulse. Defaults to 0. Must not be negative, must likewise be a whole number of sampling periods, and must not exceed one Period. It delays the output rather than postponing the generator: the cycle is still aligned to t = 0 and the first cycle's duty is read at t = 0, not at the end of the delay. With a constant duty the two are indistinguishable; with a changing one they are not.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is also the resolution of the pulse: the high time can only ever be a whole number of samples, so a coarse rate quantizes the duty heavily.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The period and the delay are baked in as whole sample counts at export time rather than exposed as tunable parameters, so the generated core carries no division and no clock arithmetic – just a counter. The exported state is that counter plus the latched duty, one value per entry. Every target evaluates the same phase + 1 ≤ duty · nPeriod test, so none of them can drift from the others on a rounding convention. The three HDL targets carry the duty comparison in simulation-only real arithmetic, quantizing only at the port boundary, as the Sine Wave block does.

Simulink bridge

Import and export, mapped to simulink/Discontinuities/PWM. "Period (s)" to Period and "Initial Delay (s)" to InitialDelay, both as plain pass-through values, so the round trip is lossless. "Sampling Time (s)" goes to SampleTime, as on every block. Two Simulink parameters are always written and have no ICore counterpart: RunAtFixedTimeIntervals is fixed to on, without which the Simulink block refuses to run under a fixed-step solver at all, and DisallowZeroDutyCycle is fixed to off, because ICore has nothing to reject – a zero duty simply holds the output low for the period.

Notes

• Stateful: a sample counter, plus one latched duty per entry.
• Discrete by nature – the output is a function of the sample index, so the block always runs at its own rate rather than being pushed through a continuous solver's stages.
• The duty is read only on the sample that opens a period. Feeding it a signal that changes faster than the period is not an error, but everything between boundaries is discarded.
• An Initial Delay longer than one Period is reported rather than approximated: the output would then be drawing on duty values more than one cycle old, which this block does not keep.
• Not linear, and so deliberately carries no state space – a switching output is not a linear map.