Dead Zone — Control Systems/Discontinuities

Control_Systems/Discontinuities/Dead_Zone · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Dead Zone

Control Systems / Discontinuities

Produces no response inside a band around zero, and outside it passes the input through shifted by the band edge: y = u − end above the band, y = u − start below it, and y = 0 inside. The output is therefore continuous but flat through the origin. Applied entry by entry, so a matrix signal is treated element for element.

Ports

Input – the signal u, of any size [m,n].
Output – the dead-zoned signal y, of the SAME size [m,n]. The block never reshapes a signal.

Parameters

Start of Dead Zone – scalar, the lower edge. Defaults to -0.5, as in Simulink.
End of Dead Zone – scalar, the upper edge. Defaults to 0.5. It must not be below the start; an inverted band is reported and the run is stopped.
Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Both edges are scalars; a per-entry band sized like the input is not implemented and is reported rather than broadcast from its first entry.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Both edges are baked into the generated code as constants at export time rather than exposed as tunable parameters, matching the Saturation block.

Simulink bridge

Import and export, mapped to simulink/Discontinuities/Dead Zone. "Start of Dead Zone" to LowerValue and "End of Dead Zone" to UpperValue, both as plain pass-through values, so the round trip is lossless. "Sampling Time (s)" goes to SampleTime, as on every block.

Notes

Algebraic, with no state.
Not linear, and so deliberately carries no state space – model reduction reports it as unmergeable rather than absorbing it and discarding the flat segment.
The band is open at its edges: an input exactly ON an edge gives zero.

Code facts#

Fact	Value
registered type	`Control_Systems/Discontinuities/Dead_Zone`
family	`Control_Systems/Discontinuities`
solver environment class	`ICoreBlock_0_Control_Systems_1_Discontinuities_2_Dead_Zone`
source	`src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Dead_Zone/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Dead_Zone.cpp`
header	`src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Dead_Zone/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Dead_Zone.h`
default size on canvas	70 × 70 px
ports at insert	1 in, 1 out
code generators implemented	`Python`, `MATLAB`, `Java`, `Rust`, `C`, `C++`, `VHDL`, `Verilog`, `SystemVerilog`, `PLC Structured Text`

Ports#

#	Direction	Signal type	Description label
1	in	`ICoreDouble`	—
2	out	`ICoreDouble`	—

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variable	Default	Simulink parameter
`Start of Dead Zone`	`-0.5`	`LowerValue`
`End of Dead Zone`	`0.5`	`UpperValue`

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#


support	`Support::Both`
Simulink path	`simulink/Discontinuities/Dead Zone`
port-count rule	`PortsParam::None`
`SampleTime` parameter	yes

ICore config	Simulink parameter	Value translation
`Start of Dead Zone`	`LowerValue`	passes through
`End of Dead Zone`	`UpperValue`	passes through

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Dead Zone block — per-entry band of zero response around the origin y = u - end when u > end; y = u - start when u < start; y = 0 in between. Applied INDEPENDENTLY to every entry of the input signal, so the output keeps the input's size. Algebraic and stateless, and deliberately carries no state space (see the header).

Code export: both edges are inlined as export-time constants, per language.

Sample results#

t	in ICoreDouble-Out-0	out ICoreDouble-Out-0
0	-2	-1.5
0.4	0.5	0
0.8	-2	-1.5
1.2	0.5	0
1.6	-2	-1.5
2	0.5	0
2.4	-2	-1.5
2.8	0.5	0
3.2	-2	-1.5
3.6	0.5	0
4	-2	-1.5
4.4	0.5	0
4.8	-2	-1.5
5.2	0.5	0

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

Stimulus	What it is	Output range
`impulse`	Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)	0 … 0.5
`ramp`	Ramp: slope 1 from t = 0	0 … 5.3
`sine`	Sine Wave: amplitude 1, 2 rad/s, no phase, no bias	-0.5 … 0.4996
`step`	Step: 0 -> 1 at t = 1 s	0 … 0.5

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discontinuities__Dead_Zone.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).