Backlash — Control Systems/Discontinuities

Control_Systems/Discontinuities/Backlash · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Backlash

Control Systems / Discontinuities

Models mechanical play – the slack in a loose gear train or a linkage. The output sits inside a band of width w centred on itself and does not move at all while the input travels within that band. Only when the input reaches a face does the output engage and follow, trailing by half the width:

u > y + w/2 → y = u − w/2
u < y − w/2 → y = u + w/2
otherwise → y holds

Unlike a Dead Zone, whose band is fixed at the origin, this band travels with the output – which is what makes the block stateful. Applied entry by entry.

Ports

Input – the driving signal u, of any size [m,n].
Output – the driven signal y, of the SAME size [m,n]. The block never reshapes a signal.

Parameters

Deadband Width – scalar w, the total play. Defaults to 1, as in Simulink. Must not be negative; zero means no play, and the block passes its input straight through.
Initial Output – scalar, where the output starts. Defaults to 0. Because the output only moves when a face is reached, this also fixes where the band initially sits.
Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Both parameters are scalars; per-entry vectors are not implemented and are reported rather than broadcast from their first entry.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Both parameters are baked in as constants at export time. The exported state is the held output itself, one value per entry, seeded with the initial output – so a generated core starts where the in-app block does.

Simulink bridge

Import and export, mapped to simulink/Discontinuities/Backlash. "Deadband Width" to BacklashWidth and "Initial Output" to InitialOutput, both as plain pass-through values, so the round trip is lossless. "Sampling Time (s)" goes to SampleTime, as on every block.

Notes

Stateful: one held output per input entry.
The comparisons are strict, so an input exactly ON a face leaves the output where it is; it engages on the next sample that passes the face.
Not linear, and so deliberately carries no state space – the band moves with the output, which no A/B/C/D can express.

Code facts#

Fact	Value
registered type	`Control_Systems/Discontinuities/Backlash`
family	`Control_Systems/Discontinuities`
solver environment class	`ICoreBlock_0_Control_Systems_1_Discontinuities_2_Backlash`
source	`src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Backlash/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Backlash.cpp`
header	`src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Discontinuities/Backlash/ICoreBlock_0_Control_Systems_1_Discontinuities_2_Backlash.h`
default size on canvas	70 × 70 px
ports at insert	1 in, 1 out
code generators implemented	`Python`, `MATLAB`, `Java`, `Rust`, `C`, `C++`, `VHDL`, `Verilog`, `SystemVerilog`, `PLC Structured Text`

Ports#

#	Direction	Signal type	Description label
1	in	`ICoreDouble`	—
2	out	`ICoreDouble`	—

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variable	Default	Simulink parameter
`Deadband Width`	`1`	`BacklashWidth`
`Initial Output`	`0`	`InitialOutput`

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#


support	`Support::Both`
Simulink path	`simulink/Discontinuities/Backlash`
port-count rule	`PortsParam::None`
`SampleTime` parameter	yes

ICore config	Simulink parameter	Value translation
`Deadband Width`	`BacklashWidth`	passes through
`Initial Output`	`InitialOutput`	passes through

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Backlash block — mechanical play, a hysteresis band that travels with the output half = width/2; u > y+half -> y = u-half; u < y-half -> y = u+half; else y holds. Stateful: the held output IS the state, seeded with "Initial Output". No state space. Same per-language state contract as Relay -- see that block for the seeding pattern.

Sample results#

The same rig also ran:

Stimulus	What it is	Output range
`impulse`	Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair)	0 … 0.5
`ramp`	Ramp: slope 1 from t = 0	0 … 5.3
`sine`	Sine Wave: amplitude 1, 2 rad/s, no phase, no bias	-0.5 … 0.4996
`table`	Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample	-1.5 … 2.5

Plotted: step — Step: 0 -> 1 at t = 1 s

Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Discontinuities__Backlash.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).