Display — Control Systems/Dashboard

Control_Systems/Dashboard/Display · 0 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Display (Dashboard)

Control Systems / Dashboard

Shows the current value of a signal it is told the name of, on its own face – without being wired to it. It has no ports at all: drop it anywhere and it reads whatever Signal names.

Ports

None. Not one input, not one output. That is what makes it a dashboard block, and it is the whole difference from Sinks/Display, which is wired.

Naming the signal to show

ICore links carry names, and that name is the selection: rename a link (its name is editable like a block's) and put that name here. A name containing / is matched against the link's full path instead, which is how two links called err in different subsystems are told apart. Matching runs over this block's own subsystem and everything below it, never above – that is exactly the set of signals a generated core contains, so this block cannot show something in the app that its exported code has no name for.

Parameters

Signal – the link name to show, for example err or Plant/u_cmd. Empty shows nothing. This names a link in the diagram, not a variable, so it is never looked up in the variables space. A name that matches no link is reported by name when the run starts.
Format – short (4 decimals), long (15), short_e / long_e (scientific), bank (2 decimals, for currency). The same five as Sinks/Display, printed through the same conversions.
Refresh Period (s) – how often the face is repainted, in wall-clock seconds, so a fast run does not turn the readout into a blur. Zero or less repaints on every sample. The final sample of a run is always shown, whatever the period.
Sampling Time (s) – how often a sample is taken. Zero or less inherits the solver's rate.

Notes

The value is one sample behind. Solver order follows input dependencies, and a block with no inputs has none – so this block runs at the head of every step and reads what its source published on the previous one. That is inherent to watching a signal instead of receiving it: use Sinks/Display where the exact sample matters.
A matrix is shown one row per line, columns separated by two spaces and no brackets – the frame already says where the value starts and stops.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The watched signal is an ordinary signal in the generated core, so each target reads it by name and prints it per step; a deployable target has no face to paint, exactly as with the Scope. PLC Structured Text emits comments only, naming the exact signal array entries to tap, since ST has no console. The one-sample shift above applies to the exported code too, and for the same reason – so the export agrees with the app.

Code-export verification

This block is excluded from the code-export verification matrix, by name, in ICoreParityRigLibrary::unriggableTypes(). The verifier records a terminal block's input signals and compares them; a block with no inputs records nothing, so a rig around it would fail all ten languages at residual 0 with "Each matrix must have at least two columns" – a red row that says nothing about the block. The exclusion is reported by exportVerify with that reason rather than dropping it silently.

Simulink bridge

None, and that is a measurement rather than a gap. Simulink's dashboard Display (BlockType=DisplayBlock) has ZERO ports of any kind and is VIRTUAL – measured on R2026a, where a model holding one and nothing else refuses to run with "contains no blocks or all blocks are virtual". It reaches its signal through Binding, a canvas selection stored outside the block's parameters, and ICore has no counterpart for that. This block is the ICore reading of it – the signal is named rather than clicked – so it is a DIFFERENT block from the Simulink one rather than a mapping of it, and it is reported on exchange rather than asserted. Note that Sinks/Display is the block that maps to simulink/Sinks/Display; this one deliberately maps to nothing.

Code facts#

Fact	Value
registered type	`Control_Systems/Dashboard/Display`
family	`Control_Systems/Dashboard`
solver environment class	`ICoreBlock_0_Control_Systems_1_Dashboard_2_Display`
source	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Dashboard/Display/ICoreBlock_0_Control_Systems_1_Dashboard_2_Display.cpp`
header	`src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Dashboard/Display/ICoreBlock_0_Control_Systems_1_Dashboard_2_Display.h`
default size on canvas	90 × 50 px
ports at insert	0 in, 0 out
code generators implemented	`Python`, `MATLAB`, `Java`, `Rust`, `C`, `C++`, `VHDL`, `Verilog`, `SystemVerilog`, `PLC Structured Text`

Ports#

The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 0 out) or from the block's configuration.

Configuration variables#

Config variable	Default	Simulink parameter
`Signal`	—	—
`Format`	`short%~%long%~%short_e%~%long_e%~%bank~~short`	—
`Refresh Period (s)`	`0.1`	—

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#


support	`Support::None`
Simulink path	—
port-count rule	`PortsParam::None`
`SampleTime` parameter	yes

Caveat (shown to the user): Simulink's dashboard Display (BlockType=DisplayBlock) has ZERO ports of any kind and is VIRTUAL - measured on R2026a, where a model holding one and nothing else refuses to run with "contains no blocks or all blocks are virtual". It does not receive its value on a wire: it reaches the signal through Binding, a canvas selection stored outside the block's parameters, and ICore has no counterpart for that. This block is the ICore reading of that control - the signal is named rather than clicked - so it is a DIFFERENT block from the Simulink one rather than a mapping of it, and it is reported on exchange rather than asserted. There is also nothing to compare against: the Simulink block is virtual, so no simulation of it produces a sample. Use Control_Systems/Sinks/Display, which is wired, where a model must cross to simulink/Sinks/Display

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:

B0 no sample under docs/generated/samples/ — nothing to cross-check (P8.1)

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Dashboard Display -- a readout BOUND to a signal by name, with no ports at all It shows the value of the link named in "Signal" on its own face, formatted by "Format". No input port, no output port: the binding is the name, resolved at run start against the block's own subsystem and everything below it.

⚠ THERE IS NO SIMULINK COUNTERPART TO MAP ONTO, AND THAT IS A MEASUREMENT RATHER THAN A GAP. R2026a, measured on 2026-09-17: simulink_hmi_blocks/Display reports BlockType=DisplayBlock, ZERO ports of any kind, NO SampleTime, and a model holding one and nothing else refuses to run -- "contains no blocks or all blocks are virtual". Its signal arrives through Binding, a canvas selection stored outside the block's parameters. So this block is the reading of that control which this tree's signal model can express, the catalog entry is Support::None with that measurement as its reason, and no parity testbench is owed or possible: a virtual block produces no sample to compare against at any quality of implementation.

It is NOT Sinks/Display, which is wired and takes an input port. Same readout, different binding -- the Scope / Floating Scope pair exactly, and this block's resolution machinery is Floating_Scope's.

Sample results#

No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.